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Added support for non-const === and !== (for miter circuits)

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Clifford Wolf 2013-12-27 14:20:15 +01:00
parent ecc30255ba
commit 369bf81a70
10 changed files with 128 additions and 20 deletions
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36
techlibs/common/simlib.v
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@ -376,6 +376,42 @@ endmodule
// --------------------------------------------------------
module \$eqx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
`INPUT_A
`INPUT_B
output [Y_WIDTH-1:0] Y;
assign Y = A_BUF.val === B_BUF.val;
endmodule
// --------------------------------------------------------
module \$nex (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
`INPUT_A
`INPUT_B
output [Y_WIDTH-1:0] Y;
assign Y = A_BUF.val !== B_BUF.val;
endmodule
// --------------------------------------------------------
module \$ge (A, B, Y);
parameter A_SIGNED = 0;

50
techlibs/common/stdcells.v
View file

@ -572,6 +572,56 @@ endmodule
// --------------------------------------------------------
module \$eqx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = ~|(A_buf ^ B_buf);
endmodule
// --------------------------------------------------------
module \$nex (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = |(A_buf ^ B_buf);
endmodule
// --------------------------------------------------------
module \$ge (A, B, Y);
parameter A_SIGNED = 0;