Eddie Hung
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505557e93e
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Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
opt_merge: discard \init of '$' cells with 'Q' port when merging
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2020-02-05 14:56:26 -08:00 |
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Eddie Hung
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0b308c6835
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abc9_ops: -reintegrate to use derived_type for box_ports
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2020-02-05 14:46:48 -08:00 |
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Eddie Hung
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5ebdc0f8e0
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Merge pull request #1638 from YosysHQ/eddie/fix1631
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
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2020-02-05 19:31:18 +01:00 |
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Eddie Hung
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0671ae7d79
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Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
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2020-02-05 18:59:40 +01:00 |
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Marcelina Kościelnicka
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34d2fbd2f9
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Add opt_lut_ins pass. (#1673)
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2020-02-03 14:57:17 +01:00 |
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David Shah
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4bfd2ef4f3
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sv: Improve handling of wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
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2020-02-02 16:12:33 +00:00 |
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David Shah
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7e741714df
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hierarchy: Correct handling of wildcard port connections with default values
Signed-off-by: David Shah <dave@ds0.me>
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2020-02-02 16:12:33 +00:00 |
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David Shah
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5df591c023
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hierarchy: Resolve SV wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
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2020-02-02 16:12:33 +00:00 |
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David Shah
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1055b6b1dd
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Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly
synth_xilinx: add -dsp-multonly
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2020-02-02 14:53:32 +00:00 |
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David Shah
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65716c9982
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xilinx_dsp: Add multonly scratchpad var to bypass
Signed-off-by: David Shah <dave@ds0.me>
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2020-02-01 15:30:43 +00:00 |
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Eddie Hung
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136842b1ef
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Merge branch 'master' into eddie/submod_po
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2020-02-01 02:14:19 -08:00 |
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Gabriel Somlo
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8106c3d31b
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abc9: restore ability to use ABCEXTERNAL
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2020-01-30 15:12:43 -05:00 |
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Claire Wolf
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1679682fa3
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Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
Also some minor fixes to the original PR.
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2020-01-29 17:01:24 +01:00 |
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Claire Wolf
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4d0118d0c1
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Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check
opt_reduce: Call check() per run rather than per optimised cell
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2020-01-29 15:27:11 +01:00 |
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Eddie Hung
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a855f23f22
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Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
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2020-01-28 12:46:18 -08:00 |
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Eddie Hung
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7939727d14
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Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
Unpermute LUT ordering for ice40/ecp5/xilinx
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2020-01-28 11:55:51 -08:00 |
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Claire Wolf
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4ddaa70fd6
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Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
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2020-01-28 17:40:28 +01:00 |
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N. Engelhardt
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086c133ea5
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Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
synth_xilinx: error out if tristate without '-iopad'
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2020-01-28 17:24:54 +01:00 |
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David Shah
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6fd9cae5ca
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opt_reduce: Call check() per run rather than per optimised cell
Signed-off-by: David Shah <dave@ds0.me>
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2020-01-28 09:42:01 +00:00 |
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Pepijn de Vos
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409e532433
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redirect fuser stderr to /dev/null
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2020-01-28 10:02:41 +01:00 |
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Eddie Hung
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21ce1b37fb
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abc9_ops: -check for negative arrival/required times
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2020-01-27 14:22:46 -08:00 |
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Eddie Hung
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e18aeda7ed
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Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
Just like Verilog...
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2020-01-27 14:02:13 -08:00 |
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Eddie Hung
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48f3f5213e
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Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
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2020-01-27 13:29:15 -08:00 |
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Eddie Hung
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f2576c096c
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Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
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2020-01-27 12:29:28 -08:00 |
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Eddie Hung
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9009b76a69
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abc9_ops: add comments
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2020-01-27 11:18:21 -08:00 |
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Eddie Hung
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b178761551
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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
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2020-01-24 11:59:48 -08:00 |
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Eddie Hung
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dbf351390e
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abc9: -reintegrate recover type from existing cell, check against boxid
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2020-01-23 22:45:34 -08:00 |
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Eddie Hung
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245873d42d
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abc9: warning message if no modules selected
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2020-01-23 19:08:51 -08:00 |
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Eddie Hung
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f180dba753
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abc9_ops: -prep_xaiger to skip (* keep *) cells
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2020-01-23 18:56:06 -08:00 |
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Eddie Hung
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1d4314d888
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abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_*
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2020-01-23 14:58:56 -08:00 |
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Eddie Hung
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af0e7637a2
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alumacc: undo accidental commit
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2020-01-22 20:54:03 -08:00 |
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Eddie Hung
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8eb5bb258c
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Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor
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2020-01-22 12:30:14 -08:00 |
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Eddie Hung
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a94b41011d
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abc9: error out if flip-flop init is 1'b1 for '-dff'
Due to ABC sequential synthesis restriction
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2020-01-22 10:08:48 -08:00 |
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Eddie Hung
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3b44b53e94
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abc9: fix scratchpad entry abc9.verify
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2020-01-22 09:36:54 -08:00 |
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Eddie Hung
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3d9737c1bd
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
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2020-01-21 16:27:40 -08:00 |
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Claire Wolf
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5791c52e1b
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Merge pull request #1637 from YosysHQ/mwk/fix-1634
fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
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2020-01-21 18:37:06 +01:00 |
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Claire Wolf
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f165a74824
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Merge pull request #1621 from YosysHQ/clifford/fminit
Add fminit pass
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2020-01-20 22:01:57 +01:00 |
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Eddie Hung
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6a163b5ddd
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xilinx_dsp: another typo; move xilinx specific test
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2020-01-17 17:07:03 -08:00 |
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Eddie Hung
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db68e4c2a7
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ice40_dsp: fix typo
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2020-01-17 16:08:04 -08:00 |
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Eddie Hung
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e17f3f8c63
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Consistency
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2020-01-17 16:06:20 -08:00 |
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Eddie Hung
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ee500b6d8e
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xilinx_dsp: add parameter defaults
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2020-01-17 16:05:10 -08:00 |
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Eddie Hung
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4985318263
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ice40_dsp: add default values for parameters
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2020-01-17 15:37:52 -08:00 |
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Eddie Hung
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6692e5d558
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ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs
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2020-01-17 15:28:02 -08:00 |
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Eddie Hung
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d4e188299b
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abc9: add some log_{push,pop}() as per @nakengelhardt
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2020-01-17 12:00:14 -08:00 |
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Eddie Hung
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5a63c19747
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abc9_ops: -write_box is empty, output a dummy box to prevent ABC error
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2020-01-15 13:14:48 -08:00 |
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Eddie Hung
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e30b6bbbf8
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clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
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2020-01-15 09:51:31 -08:00 |
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Eddie Hung
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485e08e436
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abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)
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2020-01-14 16:33:41 -08:00 |
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Eddie Hung
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f60e071e1c
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abc9_ops: -check to check abc9_{arrival,required}
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2020-01-14 15:24:44 -08:00 |
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Eddie Hung
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1c88a6c240
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abc9_ops: implement a requireds_cache
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2020-01-14 15:20:04 -08:00 |
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Eddie Hung
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0e4285ca0d
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abc9_ops: generate flop box ids, add abc9_required to FD* cells
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2020-01-14 15:05:49 -08:00 |
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