Akash Levy
707970e300
Merge pull request #34 from alaindargelas/opt_balance_tree_off_chain
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opt_balance_tree allow_off_chain
2024-12-13 02:21:29 -08:00
Akash Levy
1242db626f
Merge remote-tracking branch 'upstream/main'
2024-12-12 22:49:19 -08:00
github-actions[bot]
4581f75b03
Bump version
2024-12-13 00:23:01 +00:00
Alain Dargelas
41c6b71bcb
opt_balance_tree allow_off_chain
2024-12-12 09:50:53 -08:00
N. Engelhardt
f384eac28b
Merge pull request #4815 from YosysHQ/verific_bounds_fix
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Verific frontend: fix `top_bound`/`bottom_bound` attributes
2024-12-12 12:59:55 +01:00
N. Engelhardt
378864d33b
bound attributes: handle vhdl null ranges
2024-12-12 11:42:39 +01:00
github-actions[bot]
e32e199ca8
Bump version
2024-12-12 00:22:44 +00:00
Akash Levy
713f80e850
Merge pull request #33 from alaindargelas/activity_info
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Activity info
2024-12-11 12:01:20 -08:00
Akash Levy
caaef5ac14
Merge branch 'YosysHQ:main' into main
2024-12-11 12:00:34 -08:00
Alain Dargelas
fc63cd7f58
Activity info and rename cmd
2024-12-11 11:04:53 -08:00
Alain Dargelas
88ff296657
Activity info and rename cmd
2024-12-11 11:04:35 -08:00
N. Engelhardt
03033ab6d4
add more tests for bounds attributes, fix attributes appearing in verilog
2024-12-11 16:11:02 +01:00
Miodrag Milanovic
e91e95f501
Next dev cycle
2024-12-11 09:01:32 +01:00
Miodrag Milanovic
aaa5347494
Release version 0.48
2024-12-11 08:35:36 +01:00
github-actions[bot]
1f6153a55a
Bump version
2024-12-11 00:22:54 +00:00
Martin Povišer
4bd6061709
Merge pull request #4799 from povik/wrapcell-unused
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wrapcell: Optionally track unused outputs
2024-12-10 21:16:28 +01:00
Martin Povišer
3ce7283e12
Merge pull request #4809 from povik/rm-global-tcl-h
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kernel: Remove global `tcl.h` include
2024-12-10 20:36:34 +01:00
Martin Povišer
86fad8f6f5
Merge pull request #4803 from povik/write_verilog-buf
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write_verilog: Use assign for `$buf`
2024-12-10 20:10:58 +01:00
Martin Povišer
f7ad003a6f
Merge pull request #4802 from povik/abc9-box-repeat
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Adjust `abc9_ops -prep_box` to allow repeated invocation
2024-12-10 20:08:17 +01:00
Martin Povišer
ea38fcca5e
Merge pull request #4737 from povik/abc_new-design-boxes
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Support `abc9_box` on ordinary modules in abc_new
2024-12-10 20:07:56 +01:00
Martin Povišer
e9c7967d1e
Merge pull request #4804 from povik/read_liberty-comb-cells
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read_liberty: Revisit for abc9 whiteboxes
2024-12-10 17:50:21 +01:00
Emil J
aed32a1df4
Merge pull request #4810 from YosysHQ/emil/fix-dfflibmap-test
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tests: fix dfflibmap test
2024-12-10 17:46:11 +01:00
Emil J. Tywoniak
55dcf0e200
tests: fix dfflibmap test - false negative conflict multiple -liberty vs enable inference
2024-12-10 15:48:23 +01:00
Martin Povišer
48c8d70a45
wrapcell: Test check -assert post wrapping
2024-12-10 15:13:31 +01:00
Martin Povišer
3cd01a57cd
wrapcell: Add comments, const qualifier
2024-12-10 15:13:31 +01:00
Martin Povišer
0bb139dc25
abc_new: Fix help crash
2024-12-10 14:27:55 +01:00
Martin Povišer
6b343c2600
aiger2: Clean debug print
2024-12-10 14:27:55 +01:00
Martin Povišer
559209c856
abc_new: Fix PI confusion in whitebox model export
2024-12-10 14:27:29 +01:00
Martin Povišer
2a3f60bc06
abc_new: Support abc9_box mode on ordinary design hierarchy
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Previously the `abc9_box` mode was reserved to modules with the
`blackbox` or `whitebox` attribute. Allow `abc9_box` on ordinary modules
when doing hierarchical synthesis.
2024-12-10 14:27:29 +01:00
Martin Povišer
285f24d764
abc_new: Support per-module script override
2024-12-10 14:27:29 +01:00
Martin Povišer
495a7805ec
aiger2: Support $extern: hierarchy
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`$extern:...` modules inserted by `techmap -extern` are special in the
regard that they have a private ID (starting with a dollar sign) but are
not an internal cell. Support those modules in xaiger export.
2024-12-10 14:27:29 +01:00
Martin Povišer
1f718e3ab6
kernel: Remove global tcl.h include
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In commit ac988cf#4808 ).
One way out is to avoid a global `tcl.h` include. In the process we drop
support for Tcl-enabled MXE builds, which were likely broken anyway due
to the additional Tcl APIs used from `tclapi.cc`.
2024-12-10 13:49:08 +01:00
Emil J
87736a2bf9
Merge pull request #4807 from YosysHQ/emil/dfflibmap-test-dffe
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dfflibmap: cover enable inference with test
2024-12-10 12:41:11 +01:00
Akash Levy
d8fcc36f65
Smallfix
2024-12-09 19:09:29 -08:00
Akash Levy
78ceb23022
Use tcl.h instead
2024-12-09 17:32:25 -08:00
Akash Levy
1d0570a52c
Small tclapi fix
2024-12-09 16:46:06 -08:00
Akash Levy
5dcdb5060c
Fix share destdir
2024-12-09 13:29:34 -08:00
Akash Levy
2c5811daa1
Fix warnings
2024-12-09 11:45:09 -08:00
Akash Levy
e0ba08dd1d
Merge branch 'YosysHQ:main' into main
2024-12-09 11:13:47 -08:00
Martin Povišer
b0708a38bf
Merge pull request #4678 from povik/tcl-rtlil-api
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Start Tcl design inspection methods
2024-12-09 15:44:58 +01:00
Martin Povišer
a353b8fff0
read_liberty: Directly set abc9_box on fitting cells
2024-12-09 15:43:41 +01:00
Martin Povišer
9161377c5a
wrapcell: Fix help
2024-12-09 15:40:33 +01:00
Miodrag Milanović
d0f239a0c4
Merge pull request #4806 from YosysHQ/micko/verific_blackbox
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verific: Disable module existence check during static elaboration
2024-12-09 15:13:34 +01:00
Martin Povišer
481162b848
Merge pull request #4800 from povik/portarcs-fix
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Fix portarcs edge cases
2024-12-09 15:13:15 +01:00
Emil J. Tywoniak
681b678417
dfflibmap: cover enable inference with test
2024-12-09 14:18:08 +01:00
Akash Levy
8bb193d7c5
Merge branch 'YosysHQ:main' into main
2024-12-08 15:44:46 -08:00
Miodrag Milanović
f4ddbc3994
Merge pull request #4771 from pepijndevos/famxtra
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gowin: split cells_xtra by family
2024-12-08 19:46:36 +01:00
github-actions[bot]
fa0c311862
Bump version
2024-12-07 00:22:16 +00:00
Miodrag Milanovic
05398889ad
Add verific verilog test cases for blackboxes
2024-12-06 16:13:25 +01:00
Miodrag Milanovic
7d4aff618f
verific: Disable module existence check during static elaboration
2024-12-06 15:59:09 +01:00
