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Merge pull request #4806 from YosysHQ/micko/verific_blackbox
verific: Disable module existence check during static elaboration
This commit is contained in:
Miodrag Milanović
GitHub
commit
d0f239a0c4
3 changed files with 104 additions and 23 deletions
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@ -2688,11 +2688,51 @@ struct VerificExtNets
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}
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};
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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static msg_type_t prev_1063;
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#endif
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#ifdef VERIFIC_VHDL_SUPPORT
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static msg_type_t prev_1240 ;
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static msg_type_t prev_1241 ;
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#endif
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void save_blackbox_msg_state()
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{
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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prev_1063 = Message::GetMessageType("VERI-1063") ;
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Message::SetMessageType("VERI-1063", VERIFIC_INFO);
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#endif
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#ifdef VERIFIC_VHDL_SUPPORT
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prev_1240 = Message::GetMessageType("VHDL-1240") ;
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prev_1241 = Message::GetMessageType("VHDL-1241") ;
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Message::SetMessageType("VHDL-1240", VERIFIC_INFO);
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Message::SetMessageType("VHDL-1241", VERIFIC_INFO);
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#endif
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}
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void restore_blackbox_msg_state()
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{
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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Message::ClearMessageType("VERI-1063") ;
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if (Message::GetMessageType("VERI-1063")!=prev_1063)
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Message::SetMessageType("VERI-1063", prev_1063);
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#endif
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#ifdef VERIFIC_VHDL_SUPPORT
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Message::ClearMessageType("VHDL-1240") ;
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Message::ClearMessageType("VHDL-1241") ;
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if (Message::GetMessageType("VHDL-1240")!=prev_1240)
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Message::SetMessageType("VHDL-1240", prev_1240);
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if (Message::GetMessageType("VHDL-1241")!=prev_1241)
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Message::SetMessageType("VHDL-1241", prev_1241);
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#endif
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}
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void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED)
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{
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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save_blackbox_msg_state();
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VerificExtensions::ElaborateAndRewrite(work, parameters);
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verific_error_msg.clear();
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restore_blackbox_msg_state();
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#endif
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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if (!ppfile.empty())
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@ -2823,8 +2863,10 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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if (static_elaborate) {
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save_blackbox_msg_state();
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VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, parameters);
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verific_error_msg.clear();
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restore_blackbox_msg_state();
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#endif
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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if (!ppfile.empty())
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@ -3290,10 +3332,8 @@ struct VerificPass : public Pass {
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return filename;
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}
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#ifdef VERIFIC_VHDL_SUPPORT
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msg_type_t prev_1240 ;
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msg_type_t prev_1241 ;
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#ifdef VERIFIC_VHDL_SUPPORT
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void add_units_to_map(Map &map, std::string work, bool flag_lib)
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{
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MapIter mi ;
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@ -3306,11 +3346,7 @@ struct VerificPass : public Pass {
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map.Insert(unit,unit);
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}
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}
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prev_1240 = Message::GetMessageType("VHDL-1240") ;
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prev_1241 = Message::GetMessageType("VHDL-1241") ;
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Message::SetMessageType("VHDL-1240", VERIFIC_INFO);
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Message::SetMessageType("VHDL-1241", VERIFIC_INFO);
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save_blackbox_msg_state();
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}
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void set_units_to_blackbox(Map &map, std::string work, bool flag_lib)
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@ -3325,17 +3361,10 @@ struct VerificPass : public Pass {
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unit->SetCompileAsBlackbox();
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}
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}
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Message::ClearMessageType("VHDL-1240") ;
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Message::ClearMessageType("VHDL-1241") ;
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if (Message::GetMessageType("VHDL-1240")!=prev_1240)
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Message::SetMessageType("VHDL-1240", prev_1240);
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if (Message::GetMessageType("VHDL-1241")!=prev_1241)
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Message::SetMessageType("VHDL-1241", prev_1241);
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restore_blackbox_msg_state();
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}
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#endif
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msg_type_t prev_1063;
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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void add_modules_to_map(Map &map, std::string work, bool flag_lib)
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{
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@ -3349,9 +3378,7 @@ struct VerificPass : public Pass {
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map.Insert(veri_module,veri_module);
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}
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}
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prev_1063 = Message::GetMessageType("VERI-1063") ;
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Message::SetMessageType("VERI-1063", VERIFIC_INFO);
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save_blackbox_msg_state();
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}
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void set_modules_to_blackbox(Map &map, std::string work, bool flag_lib)
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@ -3366,9 +3393,6 @@ struct VerificPass : public Pass {
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veri_module->SetCompileAsBlackbox();
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}
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}
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Message::ClearMessageType("VERI-1063") ;
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if (Message::GetMessageType("VERI-1063")!=prev_1063)
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Message::SetMessageType("VERI-1063", prev_1063);
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}
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#endif
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@ -3424,7 +3448,6 @@ struct VerificPass : public Pass {
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RuntimeFlags::SetVar("veri_preserve_assignments", 1);
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RuntimeFlags::SetVar("veri_preserve_comments", 1);
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RuntimeFlags::SetVar("veri_preserve_drivers", 1);
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RuntimeFlags::SetVar("veri_create_empty_box", 1);
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// Workaround for VIPER #13851
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RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
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17
tests/verific/blackbox_empty.ys
Normal file
17
tests/verific/blackbox_empty.ys
Normal file
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@ -0,0 +1,17 @@
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verific -sv <<EOF
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module TEST_CELL(input clk, input a, input b, output reg c);
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parameter PATH = "DEFAULT";
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endmodule
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EOF
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verific -sv <<EOF
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module top(input clk, input a, input b, output c, output d);
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TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
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TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
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endmodule
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EOF
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verific -import top
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hierarchy -top top
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stat
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select -assert-count 2 t:TEST_CELL
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41
tests/verific/blackbox_ql.ys
Normal file
41
tests/verific/blackbox_ql.ys
Normal file
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@ -0,0 +1,41 @@
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verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
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verific -sv <<EOF
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module top (
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input wire [19:0] a,
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input wire [17:0] b,
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output wire [37:0] z,
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input wire clk,
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input wire reset,
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input wire unsigned_a,
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input wire unsigned_b,
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input wire f_mode,
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input wire [2:0] output_select,
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input wire register_inputs
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);
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// module instantiation
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QL_DSP2_MULT_REGIN_REGOUT #(
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.MODE_BITS(80'h1232324)
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) u1 (
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.a (a),
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.b (b),
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.z (z),
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.clk (clk),
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.reset (reset),
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.unsigned_a (unsigned_a),
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.unsigned_b (unsigned_b),
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.f_mode (f_mode),
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.output_select (output_select),
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.register_inputs (register_inputs)
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);
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endmodule
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EOF
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verific -import top
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hierarchy -top top
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synth_quicklogic -family qlf_k6n10f
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select -assert-count 1 t:QL_DSP2_MULT_REGIN_REGOUT a:MODE_BITS=80'h1232324
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