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Author SHA1 Message Date
Miodrag Milanovic
55034dbe91 Remaining fix 2026-06-23 07:26:12 +02:00
Miodrag Milanovic
a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Miodrag Milanovic
3ac58b3ac1 Fixed line endings 2026-06-23 07:17:22 +02:00
Miodrag Milanovic
1f0ac8fffc Remove utf-8 marker 2026-06-23 07:14:20 +02:00
Miodrag Milanovic
f362e1db0e Remove executable flag from .v files 2026-06-23 07:12:43 +02:00
Akash Levy
e430753499
Merge pull request #191 from Silimate/fix_release 
ci: fix silimate release
 2026-06-22 19:42:44 -07:00
Mohamed Gaber
e804c1e3c2 ci: fix silimate release 
- add option to test release flow without pushing to main
- add cmake to musllinux
- upgrade manylinux to rh-devtoolset-11
- add llvm to macos
- made CMake no longer error on unused parameters because we have some functions that are different from upstream but we'd like to keep the same signature
 2026-06-23 05:14:22 +03:00
Akash Levy
bc56d9b3c0
Merge pull request #186 from Silimate/update_from_upstream 
chore: merge upstream
 2026-06-22 16:30:28 -07:00
KrystalDelusion
fe8f29b5f8
Merge pull request #5975 from dobios/patch-1 
[docs] nit: least/most significant bits referred to using LSB/MSB instead of LSb/MSb
 2026-06-22 23:21:34 +00:00
KrystalDelusion
e20a9168fb
Merge pull request #5971 from YosysHQ/krys/upto_indexing 
write_verilog: Fix upto indexing for single bit
 2026-06-22 23:04:16 +00:00
Krystine Sherwin
de6aa77dc8
equiv_opt: Add ignore-unknown-cells 2026-06-23 10:54:00 +12:00
Miodrag Milanović
0bd04dbae3
Merge pull request #5980 from YosysHQ/synth_intel 
synth_intel: fix broken dsp mapping
 2026-06-22 16:46:02 +00:00
Miodrag Milanovic
09eef69e31 synth_intel: fix broken dsp mapping 2026-06-22 17:51:26 +02:00
Mohamed Gaber
a8142b882f CMake: integrate backward-cpp 2026-06-22 18:24:29 +03:00
Miodrag Milanović
6edbcecc52
Merge pull request #5972 from YosysHQ/ci_mingw64 
Add mingw64 build to CI
 2026-06-22 14:54:56 +00:00
Miodrag Milanović
9139c94c8c
Merge pull request #5977 from YosysHQ/bitwuzla 
smtbmc: support latest bitwuzla
 2026-06-22 14:23:35 +00:00
Miodrag Milanovic
ed654de3d9 Add mingw64 build to CI 2026-06-22 16:22:13 +02:00
nella
57ec784983
Merge pull request #5953 from YosysHQ/nella/muxcover-enhancements 
Add muxcover x peepopt regression test (#964).
 2026-06-22 10:13:43 +00:00
nella
8f5d2d5894 Use -assert-none. 2026-06-22 11:12:00 +02:00
nella
3d0c868af0
Merge pull request #5952 from YosysHQ/nella/vector-index 
Optimize upto vector indexing (Fix #892).
 2026-06-22 09:05:26 +00:00
nella
6ffc938a75
Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup 
Add warnings and errors to `sim -r` with VCD code path
 2026-06-22 09:02:32 +00:00
Miodrag Milanović
f699624abf
Merge pull request #5978 from YosysHQ/remove_def 
Remove define since snprintf is supported in MSVC now
 2026-06-22 08:49:26 +00:00
Miodrag Milanovic
94e43f7675 Remove define since snprintf is supported in MSVC now 2026-06-22 09:50:39 +02:00
Miodrag Milanovic
ebcbc06951 smtbmc: support latest bitwuzla 2026-06-22 08:40:16 +02:00
Mohamed Gaber
0e7671c1b3 Merge remote-tracking branch 'origin/main' into update_from_upstream 2026-06-21 15:07:32 +03:00
Mohamed Gaber
2383dbda21 CMake: rework Silimate Verific file to work with Linux linker 2026-06-21 15:02:54 +03:00
Akash Levy
635c40ff46
Merge pull request #190 from Silimate/opt_first_fit_alloc 
opt_first_fit_alloc
 2026-06-21 02:06:12 -07:00
Akash Levy
8cdbd62394 opt_first_fit_alloc: address Greptile review 
- pack_lanes: assert elem_w < 32 and pack the full element width instead
  of silently dropping bits >= 31.
- Remove the dead `cell` struct member and its unused assignment in run()
  (every emit helper shadows it with its own local `cell`).
- Decorrelate the pseudo-random bc bits from en (independent mix) so they
  no longer share an LFSR bit (e.g. en[7]/bc[0] for n=8).
- Add purpose comments to fingerprint_dsel and lane_of_bit.

Declined the std::stoi/std::stoll arg-parsing suggestion: it matches the
established convention in sibling passes (opt_argmax, opt_priority_onehot).

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-06-21 01:21:06 -07:00
Akash Levy
dc995eba98 opt_first_fit_alloc 2026-06-21 00:56:39 -07:00
Amelia Dobis
41566a6b70
more typo found 2026-06-19 17:47:39 -04:00
Amelia Dobis
54d43d85e3
[docs] nit: usign the right acronym to refer to the right thing 
Tiny nit, but the description of `RTLIL::Wire` was using MSB and LSB to refer to the least and most significant *bits* of a wire and not Bytes, which should be referred to using LSb and MSb instead
 2026-06-19 17:30:28 -04:00
Krystine Sherwin
b77bb851ed
tests: Add mixed_upto write_verilog test 2026-06-19 11:20:01 +12:00
Krystine Sherwin
338d4adef2
write_verilog: Fix upto indexing for single bit 2026-06-19 10:18:27 +12:00
Mohamed Gaber
9316df4480
ci: update release flow 2026-06-19 01:17:40 +03:00
Mohamed Gaber
4db5fe5f6d
Merge remote-tracking branch 'silimate/main' into update_from_upstream 2026-06-19 00:07:08 +03:00
Mohamed Gaber
d423c5c03a
chore: disable failing tests until we can take a deeper look at them 2026-06-18 23:02:21 +03:00
nella
5d7486115a
Merge pull request #5887 from YosysHQ/nella/fix-signedness-4402 
Fix: `read_verilog` doesn't respect `signed` keyword
 2026-06-18 16:53:37 +00:00
nella
2195277b5a
Merge pull request #5960 from YosysHQ/nella/latch-infer 
proc_dlatch - infer $adlatch (Fix #5910).
 2026-06-18 16:50:48 +00:00
nella
c99a037c33
Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745 
Fix  `chparam` values are unsigned when using read_verilog frontend
 2026-06-18 16:50:22 +00:00
Akash Levy
fe9689eaaf Small update 2026-06-18 05:26:28 -07:00
Miodrag Milanović
c9805ceb33
Merge pull request #5966 from maliberty/lz4-1.10.0-cve 
Update lz4 to 1.10.0 for CVE-2014-4715, CVE-2021-3520, CVE-2019-17543
 2026-06-18 11:32:12 +00:00
Akash Levy
db7cfd404d Fix cut_region.h debug 2026-06-18 04:02:52 -07:00
Akash Levy
9c80f1443c
Merge pull request #189 from Silimate/opt_carry_select 
opt_carry_select pass
 2026-06-18 04:01:39 -07:00
nella
46cbeab720 Add effort limit. 2026-06-18 11:58:01 +02:00
nella
75a30a22d6 Cleanup bitsim, document hypo. 2026-06-18 11:43:13 +02:00
Akash Levy
9df378f8ac opt_carry_select pass 2026-06-18 02:36:29 -07:00
nella
25810193ab Reuse sat/hashlib. 2026-06-18 10:57:20 +02:00
Matt Liberty
7fbeb344a4 Update lz4 to 1.10.0 for CVE-2014-4715, CVE-2021-3520, CVE-2019-17543 
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
 2026-06-18 07:00:59 +00:00
Miodrag Milanović
72f6df873a
Merge pull request #5964 from YosysHQ/mingw_fix 
Fix share lookup for mingw builds
 2026-06-17 18:32:02 +00:00