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Author SHA1 Message Date
Akash Levy
5e7e172570
Merge pull request #133 from Silimate/sim 
Better support for arrays in RTL + VCD
 2026-03-30 15:12:11 -07:00
Stan Lee
d2cd4d2cc8 Merge branch 'main' of github.com:silimate/yosys into sim 2026-03-30 14:48:34 -07:00
Stan Lee
c767d90f3d add warning 2026-03-30 14:13:43 -07:00
Stan Lee
e10f545c69 fixes 2026-03-30 13:13:14 -07:00
Stan Lee
857f356f1f remove ambiguity in implementation 2026-03-30 12:26:44 -07:00
Stan Lee
01f0fd751f fixes for arrays 2026-03-30 12:13:50 -07:00
Lofty
240439bdb0
Merge pull request #5781 from YosysHQ/update_abc 
Update ABC as per 2026-03-27
 2026-03-30 16:37:29 +00:00
Lofty
903695892a
Merge pull request #5784 from YosysHQ/lofty/abc-changelog 
changelog: update for abc changes
 2026-03-30 16:36:08 +00:00
Gus Smith
6a5fea1b27 Regression test for #5765 2026-03-30 08:59:28 -07:00
Lofty
0f87fd8ef6 changelog: update for abc changes 2026-03-30 15:24:07 +01:00
Miodrag Milanovic
417e871b06 Fix tests due to ABC improvements 2026-03-30 15:23:27 +01:00
Miodrag Milanovic
23cfeabfe1 Update ABC as per 2026-03-27 2026-03-30 15:23:27 +01:00
Akash Levy
3ea2b222ab
Merge pull request #131 from Silimate/miter_opt_sat 
Miter opt sat
 2026-03-27 18:08:26 -07:00
Akash Levy
f810bff900
Merge pull request #132 from Silimate/ignore_placeholder_ports 
[ENG-1827] ignore placeholder/empty ports from verific
 2026-03-27 16:41:20 -07:00
AdvaySingh1
8aebec79a8 Added -filter_non_trigger_outputs knob 2026-03-27 15:41:44 -07:00
Abhinav Tondapu
d5122ed2fa [ENG-1827] ignore placeholder/empty ports from verific 2026-03-27 15:20:12 -07:00
AdvaySingh1
ad6546b05e Revert "Update passes/techmap/abc.cc" 
This reverts commit 20cf9fb461.
 2026-03-27 14:53:38 -07:00
Advay Singh
20cf9fb461
Update passes/techmap/abc.cc 
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
 2026-03-27 12:45:57 -07:00
Miodrag Milanović
74fef31bf2
Merge pull request #5773 from rocallahan/num-active-workers 
Prevent race on `num_active_worker_threads_`.
 2026-03-27 19:23:30 +00:00
Miodrag Milanović
18bcd0b499
Merge pull request #5785 from YosysHQ/fix_ci_temp 
CI: temporary disable macos for testing
 2026-03-27 17:34:18 +00:00
Miodrag Milanovic
d37b02af03 CI: temporary disable macos for testing 2026-03-27 17:46:14 +01:00
AdvaySingh1
5c94a47298 moved verific to main head 2026-03-26 17:02:57 -07:00
AdvaySingh1
113b3e02ce Removed adding struct partition object file 2026-03-26 16:59:58 -07:00
AdvaySingh1
972e4780c9 Removed extra struct partition pass 2026-03-26 16:58:09 -07:00
AdvaySingh1
f523760b75 merged with main 2026-03-26 16:50:59 -07:00
AdvaySingh1
f42a63941c Added initial clkmerge pass for multiple clock domains 2026-03-26 16:42:27 -07:00
Akash Levy
5376dc27e1 Update Verific for bugfix 2026-03-25 22:49:17 -07:00
Akash Levy
22bfdc23a8
Merge pull request #128 from Silimate/negopt_debug_logs 
adding temp debug logs to fix runtime issue
 2026-03-25 19:07:10 -07:00
Abhinav Tondapu
510ef01b09 adding temp debug logs to fix runtime issue 2026-03-25 16:55:29 -07:00
AdvaySingh1
f84fd46a17 Added test cases for clkmerge and cone_partition passes 2026-03-25 15:06:58 -07:00
Miodrag Milanović
ebfe5b2c06
Merge pull request #5774 from Silimate/atondapu/sim-cache-sigmap 
sim: cache sigmap in register_output_step_values
 2026-03-25 06:40:01 +00:00
AdvaySingh1
92e659f42a Added new port outputs anding the clock domain. TODO: fix if they belong to the same one and there's multiple 2026-03-24 20:00:24 -07:00
tondapusili
5b22e64d19 sim: cache sigmap in register_output_step_values 2026-03-24 16:10:11 -07:00
Robert O'Callahan
290fb0556d Prevent race on num_active_worker_threads_. 
The core issue here is that we need to ensure `num_active_worker_threads_`
is read before incrementing `done_workers`. See the comments
added in this PR to explain why, and why the resulting code is
race-free.
 2026-03-24 22:20:18 +00:00
AdvaySingh1
f7a9af5252 Make the signal_map flag optional 2026-03-24 14:39:21 -07:00
Miodrag Milanović
66306a8ca3
Merge pull request #5769 from Silimate/optimize_sim_pass 
sim: early return from checkSignals in sim mode
 2026-03-23 17:19:26 +00:00
Miodrag Milanović
cc915b4c76
Merge pull request #5717 from zaun/latch-support 
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
 2026-03-23 16:51:30 +00:00
Emil J
b44188110b
Merge pull request #5764 from YosysHQ/emil/constmap-error 
constmap: error if no -cell set
 2026-03-23 15:15:04 +00:00
Akash Levy
d99ba91fe7
Merge pull request #126 from Silimate/fix_mem_crash 
Safe parameter extraction in mem_from_cell
 2026-03-23 07:39:16 -04:00
Akash Levy
0ed1f1bfa4 Smallfixes 2026-03-23 03:51:49 -07:00
Akash Levy
91739e79cb Safe parameter extraction in mem_from_cell 2026-03-23 03:30:55 -07:00
Emil J
7b2ab9b245
Merge pull request #5763 from YosysHQ/emil/c-slow-init 
genrtlil: fast memory initialization
 2026-03-23 10:21:21 +00:00
AdvaySingh1
b9ba2c3552 Checked out abc to the yosys-experimental branch 2026-03-20 15:05:03 -07:00
AdvaySingh1
f9f31afcb4 Makefile pass changes 2026-03-20 12:42:51 -07:00
AdvaySingh1
2fc0591b2c Added clkmerge pass 2026-03-20 12:42:24 -07:00
tondapusili
69219e6be0 sim: early-return from checkSignals in sim mode 2026-03-20 12:32:49 -07:00
AdvaySingh1
e2a641f5a8 Added support for printing the cdc map file 2026-03-20 11:32:06 -07:00
AdvaySingh1
59dd03973e Added printing differnt clock domains in signal map 2026-03-20 10:37:47 -07:00
AdvaySingh1
daf5108434 Added inital cone_parition.cc pass. TODO: check with larger designs 2026-03-19 16:30:11 -07:00
AdvaySingh1
1711da5506 Moved the struct_partition pass to Silimate 2026-03-19 15:06:50 -07:00