1195 commits

Author	SHA1	Message	Date
Eddie Hung	569cd66764	Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp	2019-07-16 14:18:36 -07:00
Eddie Hung	5d1ce04381	Add support for {A,B,P}REG in DSP48E1	2019-07-16 14:05:50 -07:00
whitequark	698ab9beee	synth_ecp5: rename dram to lutram everywhere.	2019-07-16 20:45:12 +00:00
whitequark	ba099bfe9b	synth_{ice40,ecp5}: more sensible pass label naming.	2019-07-16 20:41:51 +00:00
Eddie Hung	7a58ee78dc	gen_lut to return correctly sized LUT mask	2019-07-16 12:45:29 -07:00
David Shah	d38df68d26	xilinx: Add correct signed behaviour to DSP48E1 model ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-16 17:53:08 +01:00
Eddie Hung	ba8ccbdea8	Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix ... abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box	2019-07-16 08:52:14 -07:00
David Shah	95c8d27b0b	xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed) ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-16 16:47:53 +01:00
David Shah	8da4c1ad82	mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-16 16:44:40 +01:00
David Shah	7a75f5f3ac	mul2dsp: Fix indentation ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-16 16:19:32 +01:00
Eddie Hung	fd5b3593d8	Do not swap if equals	2019-07-15 16:52:37 -07:00
Eddie Hung	5f00d335d4	Oops forgot these files	2019-07-15 15:03:15 -07:00
Eddie Hung	42f8e68e76	OUT port to Y in generic DSP	2019-07-15 14:45:47 -07:00
Eddie Hung	0c7ee6d0fa	Move DSP mapping back out to dsp_map.v	2019-07-15 14:18:44 -07:00
Eddie Hung	5fb27c071b	$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark	2019-07-15 12:03:51 -07:00
Eddie Hung	91fcf034bc	Only swap if B_WIDTH > A_WIDTH	2019-07-15 11:24:11 -07:00
Eddie Hung	1793e6018a	Tidy up	2019-07-15 11:19:54 -07:00
Eddie Hung	20e3d2d9b0	Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim	2019-07-15 11:13:22 -07:00
Eddie Hung	146451a767	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-07-15 09:49:41 -07:00
Eddie Hung	d032198fac	ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT	2019-07-13 01:11:00 -07:00
Clifford Wolf	463f710066	Merge pull request #1183 from whitequark/ice40-always-relut ... synth_ice40: switch -relut to be always on	2019-07-12 10:48:00 +02:00
Eddie Hung	7a912f22b2	Use Const::from_string() not its constructor...	2019-07-12 01:32:10 -07:00
Eddie Hung	28274dfb09	Off by one	2019-07-12 01:17:53 -07:00
Eddie Hung	e0e5d7d68e	Fix spacing	2019-07-12 01:15:22 -07:00
Eddie Hung	4de03bd5e6	Remove double push	2019-07-12 01:08:48 -07:00
Eddie Hung	62ac5ebd02	Map to and from this box if -abc9	2019-07-12 00:53:01 -07:00
Eddie Hung	0f5bddcd79	ice40_opt to handle this box and opt back to SB_LUT4	2019-07-12 00:52:31 -07:00
Eddie Hung	a79ff2501e	Add new box to cells_sim.v	2019-07-12 00:52:19 -07:00
Eddie Hung	c6e16e1334	_ABC macro will map and unmap to this new box	2019-07-12 00:51:37 -07:00
Eddie Hung	fc3d74616f	Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box	2019-07-12 00:50:42 -07:00
whitequark	b700a4b1c5	synth_ice40: switch -relut to be always on.	2019-07-11 20:18:41 +00:00
whitequark	a8c5f7f41e	synth_ice40: fix help text typo. NFC.	2019-07-11 20:18:41 +00:00
Eddie Hung	19c1c3cfa3	Merge pull request #1182 from koriakin/xc6s-bram ... synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 12:55:35 -07:00
Marcin Kościelnicki	a9efacd01d	xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 21:13:12 +02:00
Marcin Kościelnicki	ce250b341c	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
Eddie Hung	b33ecd2a74	Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little	2019-07-10 16:00:03 -07:00
Eddie Hung	cea7441d8a	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-07-10 15:58:01 -07:00
Eddie Hung	bb2144ae73	Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime ... Error out if -abc9 and -retime specified	2019-07-10 14:38:13 -07:00
Eddie Hung	2f990a7319	Merge pull request #1148 from YosysHQ/xc7mux ... synth_xilinx to infer wide multiplexers using new '-widemux <min>' option	2019-07-10 14:38:00 -07:00
Eddie Hung	6bbd286e03	Error out if -abc9 and -retime specified	2019-07-10 12:47:48 -07:00
Eddie Hung	58bb84e5b2	Add some spacing	2019-07-10 12:32:33 -07:00
Eddie Hung	521971e32e	Add some ASCII art explaining mux decomposition	2019-07-10 12:20:04 -07:00
Eddie Hung	e573d024a2	Call muxpack and pmux2shiftx before cmp2lut	2019-07-09 21:26:38 -07:00
Eddie Hung	c55530b901	Restore opt_clean back to original place	2019-07-09 14:29:58 -07:00
Eddie Hung	5b48b18d29	Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6	2019-07-09 14:28:54 -07:00
David Shah	27b27b8781	synth_ecp5: Fix typo in copyright header ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-09 22:26:10 +01:00
Eddie Hung	b1a048a703	Extend using A[1] to preserve don't care	2019-07-09 12:35:41 -07:00
Eddie Hung	93522b0ae1	Extend during mux decomposition with 1'bx	2019-07-09 10:59:37 -07:00
Eddie Hung	c864995343	Fix typo and comments	2019-07-09 10:38:07 -07:00
Eddie Hung	c91cb73562	Merge remote-tracking branch 'origin/master' into xc7mux	2019-07-09 10:22:49 -07:00