mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Do not swap if equals

Browse source
This commit is contained in:
Eddie Hung 2019-07-15 16:52:37 -07:00
parent b29f26f6c7
commit fd5b3593d8
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/common/mul2dsp.v
View file

@ -33,7 +33,7 @@ module \$mul (A, B, Y);
output [Y_WIDTH-1:0] Y;
generate
if (B_WIDTH < A_WIDTH)
if (A_WIDTH >= B_WIDTH)
\$__mul_gen #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),