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Code Activity
14669 commits 122 branches 59 tags 72 MiB
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4257 commits

Author SHA1 Message Date
Clifford Wolf
afdc990595
Merge pull request #1429 from YosysHQ/clifford/checkmapped 
Add "check -mapped"
 2019-10-03 11:50:53 +02:00
Clifford Wolf
3e27b2846b Add "check -allow-tbuf" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 11:49:56 +02:00
Eddie Hung
e9645c7fa7 Fix broken CI, check reset even for constants, trim rstmux 2019-10-02 21:26:26 -07:00
Eddie Hung
c6a55d948a Merge branch 'eddie/fix_sat_init' into eddie/fix1427 2019-10-02 18:07:38 -07:00
Eddie Hung
d99810ad8a Refactor peepopt_dffmux and be sensitive to \init when trimming 2019-10-02 18:01:45 -07:00
Eddie Hung
f46ac1df9f Be mindful that sigmap(wire) could have dupes when checking \init 2019-10-02 16:08:46 -07:00
Eddie Hung
265a655ef9 Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf 2019-10-02 12:43:35 -07:00
Clifford Wolf
45e4c040d7 Add "check -mapped" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-02 13:35:03 +02:00
Eddie Hung
edc3780723 techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias 2019-09-30 17:20:12 -07:00
Eddie Hung
1b96d29174 No need to punch ports at all 2019-09-30 17:02:20 -07:00
Eddie Hung
390b960c8c Resolve FIXME on calling proc just once 2019-09-30 16:37:29 -07:00
Eddie Hung
e529872b01 Remove need for $currQ port connection 2019-09-30 16:33:40 -07:00
Eddie Hung
f2f19df2d4 Add -select option to aigmap 2019-09-30 15:26:29 -07:00
Eddie Hung
e0aa772663 Add comment 2019-09-30 15:19:02 -07:00
Eddie Hung
a6994c5f16 scc call on active module module only, plus cleanup 2019-09-30 12:57:19 -07:00
Eddie Hung
8684b58bed Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-30 12:29:35 -07:00
Eddie Hung
a274b7cc86 Update doc for equiv_opt 2019-09-30 10:59:56 -07:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in 
Open aig frontend as binary file
 2019-09-30 17:49:23 +02:00
Clifford Wolf
0d28e45dcb
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync 
equiv_opt to call async2sync when not -multiclock like SymbiYosys
 2019-09-30 17:04:21 +02:00
Clifford Wolf
10e57f3880 Fix $dlatch handling in async2sync 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-30 14:58:23 +02:00
Eddie Hung
1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Eddie Hung
5a4011e8c9 Fix "scc" call inside abc9 to consider all wires 2019-09-29 09:58:00 -07:00
Miodrag Milanovic
3f70c1fd26 Open aig frontend as binary file 2019-09-29 13:22:11 +02:00
Eddie Hung
79b6edb639 Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
Eddie Hung
313d2478e9 Split ABC9 based on clocking only, add "abc_mergeability" attr for en 2019-09-27 18:41:04 -07:00
Eddie Hung
fe722b737c Add -select option to aigmap 2019-09-27 17:44:01 -07:00
Eddie Hung
8f5710c464 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-27 15:14:31 -07:00
Eddie Hung
a39505e329 equiv_opt to call async2sync when not -multiclock like SymbiYosys 2019-09-27 12:59:10 -07:00
Eddie Hung
aebbfffd71 Ooops AREG and BREG to default to -1 2019-09-27 11:57:53 -07:00
Marcin Kościelnicki
fd0e3a2c43 Fix _TECHMAP_REMOVEINIT_ handling. 
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.

Fixes the problem identified in #1396.
 2019-09-27 18:34:12 +02:00
Eddie Hung
26657037b8 Update doc with max cascade chain of 20 2019-09-26 14:31:02 -07:00
Eddie Hung
5b9deef10d Do not always zero out C (e.g. during cascade breaks) 2019-09-26 13:59:05 -07:00
Eddie Hung
95f0dd57df Update doc 2019-09-26 13:44:41 -07:00
Eddie Hung
58f31096ab Zero out ports 2019-09-26 13:40:38 -07:00
Eddie Hung
af59856ba1 xilinx_dsp_cascade to also cascade AREG and BREG 2019-09-26 13:29:18 -07:00
Eddie Hung
832216dab0 Try recursive pmgen for P cascade 2019-09-26 12:09:57 -07:00
Eddie Hung
bd8661e024 CREG to check for \keep 2019-09-26 10:32:01 -07:00
Eddie Hung
c0bb1d22e8 Remove newline 2019-09-26 10:31:55 -07:00
Eddie Hung
f1de93edf5 Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed) 2019-09-25 22:58:03 -07:00
Eddie Hung
cd8a640989 Reject if (* init *) present 2019-09-25 18:21:08 -07:00
Eddie Hung
aeb1539818 Rework xilinx_dsp postAdd for new wreduce call 2019-09-25 17:22:30 -07:00
Eddie Hung
5f8917c984 Fix memory issue since SigSpec& could be invalidated 2019-09-25 16:45:51 -07:00
Eddie Hung
486dd7c483 unextend only used in init 2019-09-25 14:05:59 -07:00
Eddie Hung
53ea5daa42 Call 'wreduce' after mul2dsp to avoid unextend() 2019-09-25 14:04:36 -07:00
Clifford Wolf
b432c9b44b Improve "portlist" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-25 09:20:38 +02:00
Clifford Wolf
6c427d36dd Add "portlist" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-24 18:08:59 +02:00
Eddie Hung
44374b1b2b "abc_padding" attr for blackbox outputs that were padded, remove them later 2019-09-23 21:58:40 -07:00
Eddie Hung
e556d48d45 Set [AB]CASCREG to legal values 2019-09-23 16:00:11 -07:00
Eddie Hung
b824a56cde Comment to explain separating CREG packing 2019-09-23 13:58:10 -07:00