Marcelina Kościelnicka
b065e09045
sim: Use Mem helper.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
e759e301a8
clk2fflogic: Use Mem helper.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
06141db233
opt_mem: Use Mem helpers.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
21896e2a02
memory_bram: Use Mem helpers.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
1e8098279f
memory_map: Use Mem helpers.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
d390b380e1
memory_unpack: Use Mem helpers.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
e9978aaf15
memory_collect: Use Mem helpers.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
248b193d6d
memory_nordff: Use Mem helpers.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
8720482ebd
Add new helper structures to represent memories.
2020-10-21 17:51:20 +02:00
N. Engelhardt
1c96a0b1d5
use strftime instead of put_time for gcc 4.8 compatibility
2020-10-21 17:47:00 +02:00
Yosys Bot
c76d533e07
Bump version
2020-10-21 00:10:07 +00:00
clairexen
e919d0c125
Merge pull request #2405 from byuccl/fix_xilinx_cells
...
xilinx/cells_sim.v: Move signal declaration to before first use
2020-10-20 17:11:36 +02:00
clairexen
099d0c2a8a
Merge pull request #2404 from YosysHQ/claire/fixrpcargs
...
Fix argument handling in connect_rpc
2020-10-20 11:32:35 +02:00
Yosys Bot
06347b119b
Bump version
2020-10-20 00:10:06 +00:00
Jeff Goeders
8be56960a2
Move signal declarations to before first use
...
Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
2020-10-19 16:09:18 -06:00
Claire Xenia Wolf
acc9d0575b
Fix argument handling in connect_rpc
...
Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
2020-10-19 13:40:57 +02:00
Miodrag Milanović
ac0bd2ffc4
Merge pull request #2397 from daveshah1/nexus
...
synth_nexus: Initial implementation
2020-10-19 11:20:56 +02:00
N. Engelhardt
eccc48c39f
wild guessing at the problem because it builds fine on my machines
2020-10-16 18:46:59 +02:00
N. Engelhardt
668d5253a5
sim -vcd: add date, version, and option for timescale
2020-10-16 18:19:58 +02:00
Yosys Bot
4c925a3214
Bump version
2020-10-16 00:10:07 +00:00
clairexen
66769a3f6a
Merge pull request #2398 from jakobwenzel/smtbmc-escape
...
smtbmc: escape identifiers in verilog testbench
2020-10-15 18:08:59 +02:00
David Shah
4d584d9319
synth_nexus: Initial implementation
...
Signed-off-by: David Shah <dave@ds0.me>
2020-10-15 08:52:15 +01:00
Yosys Bot
84e9fa7648
Bump version
2020-10-13 00:10:06 +00:00
Miodrag Milanovic
c8f052bbe0
extend verific library API for formal apps and generators
2020-10-12 14:56:15 +02:00
Yosys Bot
c403c984dd
Bump version
2020-10-09 00:10:05 +00:00
Marcelina Kościelnicka
7670a89e1f
opt_clean: Better memory handling.
...
Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself). With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.
2020-10-08 18:05:51 +02:00
Jakob Wenzel
54166ae0c5
smtbmc: escape identifiers in verilog testbench
2020-10-06 11:27:14 +02:00
Yosys Bot
fd306b0520
Bump version
2020-10-06 00:10:06 +00:00
Miodrag Milanović
1b7ed719a5
Update required Verific version
2020-10-05 13:27:27 +02:00
Yosys Bot
5aa35b8992
Bump version
2020-10-03 00:10:06 +00:00
clairexen
73cd115e08
Merge pull request #2396 from YosysHQ/claire/empty-param
...
Ignore empty parameters in Verilog module instantiations
2020-10-02 10:16:23 +02:00
Yosys Bot
a1a3e686c7
Bump version
2020-10-02 00:10:05 +00:00
Claire Xenia Wolf
46f0932c4c
Ignore empty parameters in Verilog module instantiations
...
Fixes #2394
Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
2020-10-01 18:27:16 +02:00
clairexen
7e2fc2eaeb
Merge pull request #2378 from udif/pr_dollar_high_low
...
Added $high(), $low(), $left(), $right()
2020-10-01 18:17:36 +02:00
clairexen
2412e75495
Merge pull request #2380 from Xiretza/parallel-tests
...
Clean up and parallelize testsuite
2020-10-01 18:12:31 +02:00
David Shah
c4bfbecca6
Update .gitignore
...
Signed-off-by: David Shah <dave@ds0.me>
2020-10-01 15:53:14 +01:00
clairexen
492bd3c4c2
Merge pull request #2395 from YosysHQ/sha1_if_contain_spaces
...
Use sha1 for parameter list in case if they contain spaces
2020-10-01 14:32:43 +02:00
Yosys Bot
f9ed9786bf
Bump version
2020-10-01 00:10:08 +00:00
Miodrag Milanovic
a44c5df259
use sha1 for parameter list in case if they contain spaces
2020-09-30 09:16:59 +02:00
Miodrag Milanovic
9e00f3f141
Fixed installation dir override for Python scripts
2020-09-30 07:47:36 +02:00
Yosys Bot
5a3ac39f5f
Bump version
2020-09-30 00:10:09 +00:00
clairexen
7b9a93aa2e
Merge pull request #2393 from nakengelhardt/no_const_sensitivity
...
write_verilog: emit intermediate wire for constant values in sensitivity list
2020-09-29 17:31:01 +02:00
clairexen
e8c9e541a7
Merge pull request #2392 from YosysHQ/mmicko/hierarchy_fix
...
Validate parameters only when they are used
2020-09-29 17:21:08 +02:00
Yosys Bot
dfc43c38f8
Bump version
2020-09-29 00:10:05 +00:00
N. Engelhardt
dc4a617694
add tests
2020-09-28 18:16:08 +02:00
N. Engelhardt
8f1d53e66f
write_verilog: emit intermediate wire for constant values in sensitivity list
2020-09-28 18:11:18 +02:00
Miodrag Milanović
08eb0821c9
Merge pull request #2386 from btut/fix/pyinstallpath
...
Fixed python installation path
2020-09-28 12:54:38 +02:00
N. Engelhardt
bddd56d0c6
Merge pull request #2387 from btut/fix/pythonWrappersCXXFlags
...
Use CXXFLAGS to enable pyosys specific code before generating wrappers
2020-09-28 12:45:52 +02:00
Xiretza
bed14241ef
tests: add gitignores for auto-generated makefiles
2020-09-26 16:28:24 +02:00
Benedikt Tutzer
4892ec853b
Use CXXFLAGS to enable pyosys specific code before generating wrappers
...
The .pyh files were generated without the CXXFLAGS. This meant that code
marked by the WITH_PYTHON flag was excluded. This is fixed by adding the
flag in the rule for .pyh files.
2020-09-25 12:57:46 +02:00
