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Merge pull request #2396 from YosysHQ/claire/empty-param

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Ignore empty parameters in Verilog module instantiations
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clairexen 2020-10-02 10:16:23 +02:00 • committed by GitHub
commit 73cd115e08
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frontends/verilog/verilog_parser.y
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@ -1891,6 +1891,9 @@ cell_parameter:
astbuf1->children.push_back(node);
node->children.push_back($1);
} |
'.' TOK_ID '(' ')' {
// just ignore empty parameters
} |
'.' TOK_ID '(' expr ')' {
AstNode *node = new AstNode(AST_PARASET);
node->str = *$2;