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Merge pull request #2396 from YosysHQ/claire/empty-param
Ignore empty parameters in Verilog module instantiations
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commit
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1 changed files with 3 additions and 0 deletions
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@ -1891,6 +1891,9 @@ cell_parameter:
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astbuf1->children.push_back(node);
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node->children.push_back($1);
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} |
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'.' TOK_ID '(' ')' {
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// just ignore empty parameters
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} |
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'.' TOK_ID '(' expr ')' {
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AstNode *node = new AstNode(AST_PARASET);
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node->str = *$2;
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