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https://github.com/YosysHQ/yosys
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memory_map: Use Mem helpers.
This commit is contained in:
Marcelina Kościelnicka
parent
d390b380e1
commit
1e8098279f
1 changed files with 81 additions and 138 deletions
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@ -19,6 +19,7 @@
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include "kernel/mem.h"
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#include <sstream>
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#include <set>
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#include <stdlib.h>
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@ -97,35 +98,26 @@ struct MemoryMapWorker
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return bit.wire;
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}
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void handle_cell(RTLIL::Cell *cell)
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void handle_memory(Mem &mem)
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{
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std::set<int> static_ports;
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std::map<int, RTLIL::SigSpec> static_cells_map;
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int wr_ports = cell->parameters[ID::WR_PORTS].as_int();
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int rd_ports = cell->parameters[ID::RD_PORTS].as_int();
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int mem_size = cell->parameters[ID::SIZE].as_int();
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int mem_width = cell->parameters[ID::WIDTH].as_int();
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int mem_offset = cell->parameters[ID::OFFSET].as_int();
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int mem_abits = cell->parameters[ID::ABITS].as_int();
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SigSpec init_data = cell->getParam(ID::INIT);
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init_data.extend_u0(mem_size*mem_width, true);
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SigSpec init_data = mem.get_init_data();
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// delete unused memory cell
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if (wr_ports == 0 && rd_ports == 0) {
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module->remove(cell);
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if (mem.rd_ports.empty()) {
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mem.remove();
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return;
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}
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// check if attributes allow us to infer FFRAM for this cell
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// check if attributes allow us to infer FFRAM for this memory
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for (const auto &attr : attributes) {
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if (cell->attributes.count(attr.first)) {
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const auto &cell_attr = cell->attributes[attr.first];
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if (mem.attributes.count(attr.first)) {
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const auto &cell_attr = mem.attributes[attr.first];
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if (attr.second.empty()) {
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log("Not mapping memory cell %s in module %s (attribute %s is set).\n",
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cell->name.c_str(), module->name.c_str(), attr.first.c_str());
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log("Not mapping memory %s in module %s (attribute %s is set).\n",
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mem.memid.c_str(), module->name.c_str(), attr.first.c_str());
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return;
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}
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@ -138,11 +130,11 @@ struct MemoryMapWorker
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}
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if (!found) {
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if (cell_attr.flags & RTLIL::CONST_FLAG_STRING) {
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log("Not mapping memory cell %s in module %s (attribute %s is set to \"%s\").\n",
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cell->name.c_str(), module->name.c_str(), attr.first.c_str(), cell_attr.decode_string().c_str());
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log("Not mapping memory %s in module %s (attribute %s is set to \"%s\").\n",
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mem.memid.c_str(), module->name.c_str(), attr.first.c_str(), cell_attr.decode_string().c_str());
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} else {
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log("Not mapping memory cell %s in module %s (attribute %s is set to %d).\n",
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cell->name.c_str(), module->name.c_str(), attr.first.c_str(), cell_attr.as_int());
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log("Not mapping memory %s in module %s (attribute %s is set to %d).\n",
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mem.memid.c_str(), module->name.c_str(), attr.first.c_str(), cell_attr.as_int());
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}
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return;
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}
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@ -150,82 +142,75 @@ struct MemoryMapWorker
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}
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// all write ports must share the same clock
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RTLIL::SigSpec clocks = cell->getPort(ID::WR_CLK);
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RTLIL::Const clocks_pol = cell->parameters[ID::WR_CLK_POLARITY];
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RTLIL::Const clocks_en = cell->parameters[ID::WR_CLK_ENABLE];
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clocks_pol.bits.resize(wr_ports);
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clocks_en.bits.resize(wr_ports);
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RTLIL::SigSpec refclock;
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RTLIL::State refclock_pol = RTLIL::State::Sx;
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for (int i = 0; i < clocks.size(); i++) {
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RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(i * mem_width, mem_width);
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if (wr_en.is_fully_const() && !wr_en.as_bool()) {
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bool refclock_pol = false;
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for (int i = 0; i < GetSize(mem.wr_ports); i++) {
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auto &port = mem.wr_ports[i];
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if (port.en.is_fully_const() && !port.en.as_bool()) {
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static_ports.insert(i);
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continue;
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}
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if (clocks_en.bits[i] != RTLIL::State::S1) {
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RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(i*mem_abits, mem_abits);
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RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(i*mem_width, mem_width);
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if (wr_addr.is_fully_const()) {
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// FIXME: Actually we should check for wr_en.is_fully_const() also and
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// create a $adff cell with this ports wr_en input as reset pin when wr_en
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if (!port.clk_enable) {
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if (port.addr.is_fully_const()) {
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// FIXME: Actually we should check for port.en.is_fully_const() also and
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// create a $adff cell with this ports port.en input as reset pin when port.en
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// is not a simple static 1.
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static_cells_map[wr_addr.as_int() - mem_offset] = wr_data;
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static_cells_map[port.addr.as_int() - mem.start_offset] = port.data;
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static_ports.insert(i);
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continue;
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}
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log("Not mapping memory cell %s in module %s (write port %d has no clock).\n",
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cell->name.c_str(), module->name.c_str(), i);
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log("Not mapping memory %s in module %s (write port %d has no clock).\n",
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mem.memid.c_str(), module->name.c_str(), i);
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return;
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}
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if (refclock.size() == 0) {
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refclock = clocks.extract(i, 1);
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refclock_pol = clocks_pol.bits[i];
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refclock = port.clk;
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refclock_pol = port.clk_polarity;
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}
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if (clocks.extract(i, 1) != refclock || clocks_pol.bits[i] != refclock_pol) {
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log("Not mapping memory cell %s in module %s (write clock %d is incompatible with other clocks).\n",
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cell->name.c_str(), module->name.c_str(), i);
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if (port.clk != refclock || port.clk_polarity != refclock_pol) {
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log("Not mapping memory %s in module %s (write clock %d is incompatible with other clocks).\n",
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mem.memid.c_str(), module->name.c_str(), i);
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return;
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}
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}
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log("Mapping memory cell %s in module %s:\n", cell->name.c_str(), module->name.c_str());
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log("Mapping memory %s in module %s:\n", mem.memid.c_str(), module->name.c_str());
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std::vector<RTLIL::SigSpec> data_reg_in;
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std::vector<RTLIL::SigSpec> data_reg_out;
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int count_static = 0;
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for (int i = 0; i < mem_size; i++)
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for (int i = 0; i < mem.size; i++)
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{
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if (static_cells_map.count(i) > 0)
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{
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data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem_width));
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data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem.width));
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data_reg_out.push_back(static_cells_map[i]);
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count_static++;
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}
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else
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{
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RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), ID($dff));
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c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
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if (clocks_pol.bits.size() > 0) {
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c->parameters[ID::CLK_POLARITY] = RTLIL::Const(clocks_pol.bits[0]);
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c->setPort(ID::CLK, clocks.extract(0, 1));
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RTLIL::Cell *c = module->addCell(genid(mem.memid, "", i), ID($dff));
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c->parameters[ID::WIDTH] = mem.width;
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if (GetSize(refclock) != 0) {
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c->parameters[ID::CLK_POLARITY] = RTLIL::Const(refclock_pol);
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c->setPort(ID::CLK, refclock);
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} else {
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c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1);
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c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0));
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}
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RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width);
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RTLIL::Wire *w_in = module->addWire(genid(mem.memid, "", i, "$d"), mem.width);
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data_reg_in.push_back(RTLIL::SigSpec(w_in));
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c->setPort(ID::D, data_reg_in.back());
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std::string w_out_name = stringf("%s[%d]", cell->parameters[ID::MEMID].decode_string().c_str(), i);
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std::string w_out_name = stringf("%s[%d]", mem.memid.c_str(), i);
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if (module->wires_.count(w_out_name) > 0)
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w_out_name = genid(cell->name, "", i, "$q");
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w_out_name = genid(mem.memid, "", i, "$q");
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RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width);
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SigSpec w_init = init_data.extract(i*mem_width, mem_width);
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RTLIL::Wire *w_out = module->addWire(w_out_name, mem.width);
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SigSpec w_init = init_data.extract(i*mem.width, mem.width);
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if (!w_init.is_fully_undef())
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w_out->attributes[ID::init] = w_init.as_const();
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@ -235,76 +220,39 @@ struct MemoryMapWorker
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}
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}
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log(" created %d $dff cells and %d static cells of width %d.\n", mem_size-count_static, count_static, mem_width);
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log(" created %d $dff cells and %d static cells of width %d.\n", mem.size-count_static, count_static, mem.width);
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int count_dff = 0, count_mux = 0, count_wrmux = 0;
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for (int i = 0; i < cell->parameters[ID::RD_PORTS].as_int(); i++)
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int abits = ceil_log2(mem.size);
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for (int i = 0; i < GetSize(mem.rd_ports); i++)
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{
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RTLIL::SigSpec rd_addr = cell->getPort(ID::RD_ADDR).extract(i*mem_abits, mem_abits);
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auto &port = mem.rd_ports[i];
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if (mem.extract_rdff(i))
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count_dff++;
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RTLIL::SigSpec rd_addr = port.addr;
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rd_addr.extend_u0(abits, false);
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if (mem_offset)
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rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem_offset, GetSize(rd_addr)));
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if (mem.start_offset)
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rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem.start_offset, abits));
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std::vector<RTLIL::SigSpec> rd_signals;
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rd_signals.push_back(cell->getPort(ID::RD_DATA).extract(i*mem_width, mem_width));
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rd_signals.push_back(port.data);
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if (cell->parameters[ID::RD_CLK_ENABLE].bits[i] == RTLIL::State::S1)
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{
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RTLIL::Cell *dff_cell = nullptr;
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if (cell->parameters[ID::RD_TRANSPARENT].bits[i] == RTLIL::State::S1)
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{
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dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff));
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dff_cell->parameters[ID::WIDTH] = RTLIL::Const(mem_abits);
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dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]);
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dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1));
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dff_cell->setPort(ID::D, rd_addr);
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count_dff++;
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RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits);
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dff_cell->setPort(ID::Q, RTLIL::SigSpec(w));
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rd_addr = RTLIL::SigSpec(w);
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}
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else
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{
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dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff));
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dff_cell->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
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dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]);
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dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1));
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dff_cell->setPort(ID::Q, rd_signals.back());
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count_dff++;
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RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width);
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rd_signals.clear();
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rd_signals.push_back(RTLIL::SigSpec(w));
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dff_cell->setPort(ID::D, rd_signals.back());
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}
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SigBit en_bit = cell->getPort(ID::RD_EN).extract(i);
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if (en_bit != State::S1) {
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SigSpec new_d = module->Mux(genid(cell->name, "$rdenmux", i),
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dff_cell->getPort(ID::Q), dff_cell->getPort(ID::D), en_bit);
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dff_cell->setPort(ID::D, new_d);
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}
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}
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for (int j = 0; j < mem_abits; j++)
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for (int j = 0; j < abits; j++)
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{
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std::vector<RTLIL::SigSpec> next_rd_signals;
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for (size_t k = 0; k < rd_signals.size(); k++)
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{
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), ID($mux));
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c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
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RTLIL::Cell *c = module->addCell(genid(mem.memid, "$rdmux", i, "", j, "", k), ID($mux));
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c->parameters[ID::WIDTH] = mem.width;
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c->setPort(ID::Y, rd_signals[k]);
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c->setPort(ID::S, rd_addr.extract(mem_abits-j-1, 1));
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c->setPort(ID::S, rd_addr.extract(abits-j-1, 1));
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count_mux++;
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c->setPort(ID::A, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width));
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c->setPort(ID::B, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width));
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c->setPort(ID::A, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$a"), mem.width));
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c->setPort(ID::B, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$b"), mem.width));
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next_rd_signals.push_back(c->getPort(ID::A));
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next_rd_signals.push_back(c->getPort(ID::B));
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@ -313,38 +261,37 @@ struct MemoryMapWorker
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next_rd_signals.swap(rd_signals);
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}
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for (int j = 0; j < mem_size; j++)
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for (int j = 0; j < mem.size; j++)
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module->connect(RTLIL::SigSig(rd_signals[j], data_reg_out[j]));
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}
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log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux);
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for (int i = 0; i < mem_size; i++)
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for (int i = 0; i < mem.size; i++)
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{
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if (static_cells_map.count(i) > 0)
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continue;
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RTLIL::SigSpec sig = data_reg_out[i];
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for (int j = 0; j < cell->parameters[ID::WR_PORTS].as_int(); j++)
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for (int j = 0; j < GetSize(mem.wr_ports); j++)
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{
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RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(j*mem_abits, mem_abits);
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RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(j*mem_width, mem_width);
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RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(j*mem_width, mem_width);
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auto &port = mem.wr_ports[j];
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RTLIL::SigSpec wr_addr = port.addr;
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if (mem_offset)
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wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem_offset, GetSize(wr_addr)));
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if (mem.start_offset)
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wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem.start_offset, GetSize(wr_addr)));
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RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(i, mem_abits));
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RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(i, GetSize(wr_addr)));
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int wr_offset = 0;
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while (wr_offset < wr_en.size())
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while (wr_offset < port.en.size())
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{
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int wr_width = 1;
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RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1);
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RTLIL::SigSpec wr_bit = port.en.extract(wr_offset, 1);
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while (wr_offset + wr_width < wr_en.size()) {
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RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1);
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while (wr_offset + wr_width < port.en.size()) {
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RTLIL::SigSpec next_wr_bit = port.en.extract(wr_offset + wr_width, 1);
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if (next_wr_bit != wr_bit)
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break;
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wr_width++;
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@ -354,7 +301,7 @@ struct MemoryMapWorker
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if (wr_bit != State::S1)
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{
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), ID($and));
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RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wren", i, "", j, "", wr_offset), ID($and));
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c->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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c->parameters[ID::B_SIGNED] = RTLIL::Const(0);
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c->parameters[ID::A_WIDTH] = RTLIL::Const(1);
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@ -363,17 +310,17 @@ struct MemoryMapWorker
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c->setPort(ID::A, w);
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c->setPort(ID::B, wr_bit);
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w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"));
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w = module->addWire(genid(mem.memid, "$wren", i, "", j, "", wr_offset, "$y"));
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c->setPort(ID::Y, RTLIL::SigSpec(w));
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}
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), ID($mux));
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RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wrmux", i, "", j, "", wr_offset), ID($mux));
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c->parameters[ID::WIDTH] = wr_width;
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c->setPort(ID::A, sig.extract(wr_offset, wr_width));
|
||||
c->setPort(ID::B, wr_data.extract(wr_offset, wr_width));
|
||||
c->setPort(ID::B, port.data.extract(wr_offset, wr_width));
|
||||
c->setPort(ID::S, RTLIL::SigSpec(w));
|
||||
|
||||
w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width);
|
||||
w = module->addWire(genid(mem.memid, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width);
|
||||
c->setPort(ID::Y, w);
|
||||
|
||||
sig.replace(wr_offset, w);
|
||||
|
|
@ -387,17 +334,13 @@ struct MemoryMapWorker
|
|||
|
||||
log(" write interface: %d write mux blocks.\n", count_wrmux);
|
||||
|
||||
module->remove(cell);
|
||||
mem.remove();
|
||||
}
|
||||
|
||||
void run()
|
||||
{
|
||||
std::vector<RTLIL::Cell*> cells;
|
||||
for (auto cell : module->selected_cells())
|
||||
if (cell->type == ID($mem))
|
||||
cells.push_back(cell);
|
||||
for (auto cell : cells)
|
||||
handle_cell(cell);
|
||||
for (auto &mem : Mem::get_selected_memories(module))
|
||||
handle_memory(mem);
|
||||
}
|
||||
};
|
||||
|
||||
|
|
@ -430,7 +373,7 @@ struct MemoryMapPass : public Pass {
|
|||
bool attr_icase = false;
|
||||
dict<RTLIL::IdString, std::vector<RTLIL::Const>> attributes;
|
||||
|
||||
log_header(design, "Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
|
||||
log_header(design, "Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue