mirror of
https://github.com/YosysHQ/yosys
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memory_bram: Use Mem helpers.
This commit is contained in:
Marcelina Kościelnicka
parent
1e8098279f
commit
21896e2a02
1 changed files with 90 additions and 121 deletions
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@ -18,6 +18,7 @@
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*/
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#include "kernel/yosys.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -400,9 +401,11 @@ struct rules_t
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}
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};
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bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, const rules_t::match_t &match, dict<string, int> &match_properties, int mode)
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bool replace_memory(Mem &orig_mem, const rules_t &rules, const rules_t::bram_t &bram, const rules_t::match_t &match, dict<string, int> &match_properties, int mode)
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{
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Module *module = cell->module;
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// We will modify ports — make a copy of the structure.
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Mem mem(orig_mem);
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Module *module = mem.module;
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auto portinfos = bram.make_portinfos();
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int dup_count = 1;
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@ -437,46 +440,17 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant);
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// bram.dump_config();
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int mem_size = cell->getParam(ID::SIZE).as_int();
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int mem_abits = cell->getParam(ID::ABITS).as_int();
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int mem_width = cell->getParam(ID::WIDTH).as_int();
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// int mem_offset = cell->getParam(ID::OFFSET).as_int();
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bool cell_init = !SigSpec(cell->getParam(ID::INIT)).is_fully_undef();
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bool cell_init = !mem.inits.empty();
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vector<Const> initdata;
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if (cell_init) {
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Const initparam = cell->getParam(ID::INIT);
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initdata.reserve(mem_size);
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for (int i=0; i < mem_size; i++)
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initdata.push_back(initparam.extract(mem_width*i, mem_width, State::Sx));
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Const initparam = mem.get_init_data();
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initdata.reserve(mem.size);
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for (int i=0; i < mem.size; i++)
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initdata.push_back(initparam.extract(mem.width*i, mem.width, State::Sx));
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}
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int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
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auto wr_clken = SigSpec(cell->getParam(ID::WR_CLK_ENABLE));
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auto wr_clkpol = SigSpec(cell->getParam(ID::WR_CLK_POLARITY));
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wr_clken.extend_u0(wr_ports);
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wr_clkpol.extend_u0(wr_ports);
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SigSpec wr_en = cell->getPort(ID::WR_EN);
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SigSpec wr_clk = cell->getPort(ID::WR_CLK);
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SigSpec wr_data = cell->getPort(ID::WR_DATA);
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SigSpec wr_addr = cell->getPort(ID::WR_ADDR);
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int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
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auto rd_clken = SigSpec(cell->getParam(ID::RD_CLK_ENABLE));
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auto rd_clkpol = SigSpec(cell->getParam(ID::RD_CLK_POLARITY));
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auto rd_transp = SigSpec(cell->getParam(ID::RD_TRANSPARENT));
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rd_clken.extend_u0(rd_ports);
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rd_clkpol.extend_u0(rd_ports);
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rd_transp.extend_u0(rd_ports);
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SigSpec rd_en = cell->getPort(ID::RD_EN);
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SigSpec rd_clk = cell->getPort(ID::RD_CLK);
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SigSpec rd_data = cell->getPort(ID::RD_DATA);
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SigSpec rd_addr = cell->getPort(ID::RD_ADDR);
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if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && wr_ports > 0)
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if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && !mem.wr_ports.empty())
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{
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int bucket_size = bram.dbits / portinfos.at(match.shuffle_enable - 'A').enable;
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log(" Shuffle bit order to accommodate enable buckets of size %d..\n", bucket_size);
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@ -487,23 +461,23 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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std::vector<SigSpec> old_wr_data;
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std::vector<SigSpec> old_rd_data;
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for (int i = 0; i < wr_ports; i++) {
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old_wr_en.push_back(wr_en.extract(i*mem_width, mem_width));
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old_wr_data.push_back(wr_data.extract(i*mem_width, mem_width));
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for (auto &port : mem.wr_ports) {
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old_wr_en.push_back(port.en);
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old_wr_data.push_back(port.data);
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}
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for (int i = 0; i < rd_ports; i++)
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old_rd_data.push_back(rd_data.extract(i*mem_width, mem_width));
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for (auto &port : mem.rd_ports)
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old_rd_data.push_back(port.data);
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// analyze enable structure
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std::vector<SigSpec> en_order;
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dict<SigSpec, vector<int>> bits_wr_en;
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for (int i = 0; i < mem_width; i++) {
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for (int i = 0; i < mem.width; i++) {
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SigSpec sig;
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for (int j = 0; j < wr_ports; j++)
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sig.append(old_wr_en[j][i]);
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for (auto &port : mem.wr_ports)
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sig.append(port.en[i]);
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if (bits_wr_en.count(sig) == 0)
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en_order.push_back(sig);
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bits_wr_en[sig].push_back(i);
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@ -518,7 +492,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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std::vector<int> shuffle_map;
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if (cell_init)
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new_initdata.resize(mem_size);
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new_initdata.resize(mem.size);
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for (auto &it : en_order)
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{
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@ -528,29 +502,29 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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SigBit fillbit;
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for (int i = 0; i < GetSize(bits); i++) {
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for (int j = 0; j < wr_ports; j++) {
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for (int j = 0; j < GetSize(mem.wr_ports); j++) {
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new_wr_en[j].append(old_wr_en[j][bits[i]]);
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new_wr_data[j].append(old_wr_data[j][bits[i]]);
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fillbit = old_wr_en[j][bits[i]];
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}
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for (int j = 0; j < rd_ports; j++)
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for (int j = 0; j < GetSize(mem.rd_ports); j++)
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new_rd_data[j].append(old_rd_data[j][bits[i]]);
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if (cell_init) {
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for (int j = 0; j < mem_size; j++)
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for (int j = 0; j < mem.size; j++)
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new_initdata[j].push_back(initdata[j][bits[i]]);
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}
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shuffle_map.push_back(bits[i]);
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}
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for (int i = 0; i < fillbits; i++) {
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for (int j = 0; j < wr_ports; j++) {
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for (int j = 0; j < GetSize(mem.wr_ports); j++) {
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new_wr_en[j].append(fillbit);
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new_wr_data[j].append(State::S0);
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}
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for (int j = 0; j < rd_ports; j++)
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for (int j = 0; j < GetSize(mem.rd_ports); j++)
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new_rd_data[j].append(State::Sx);
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if (cell_init) {
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for (int j = 0; j < mem_size; j++)
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for (int j = 0; j < mem.size; j++)
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new_initdata[j].push_back(State::Sx);
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}
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shuffle_map.push_back(-1);
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@ -564,40 +538,38 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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// update mem_*, wr_*, and rd_* variables
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mem_width = GetSize(new_wr_en.front());
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wr_en = SigSpec(0, wr_ports * mem_width);
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wr_data = SigSpec(0, wr_ports * mem_width);
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rd_data = SigSpec(0, rd_ports * mem_width);
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mem.width = GetSize(new_wr_en.front());
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for (int i = 0; i < wr_ports; i++) {
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wr_en.replace(i*mem_width, new_wr_en[i]);
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wr_data.replace(i*mem_width, new_wr_data[i]);
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for (int i = 0; i < GetSize(mem.wr_ports); i++) {
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auto &port = mem.wr_ports[i];
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port.en = new_wr_en[i];
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port.data = new_wr_data[i];
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}
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for (int i = 0; i < rd_ports; i++)
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rd_data.replace(i*mem_width, new_rd_data[i]);
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for (int i = 0; i < GetSize(mem.rd_ports); i++) {
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auto &port = mem.rd_ports[i];
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port.data = new_rd_data[i];
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}
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if (cell_init) {
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for (int i = 0; i < mem_size; i++)
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for (int i = 0; i < mem.size; i++)
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initdata[i] = Const(new_initdata[i]);
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}
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}
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// assign write ports
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pair<SigBit, bool> wr_clkdom;
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for (int cell_port_i = 0, bram_port_i = 0; cell_port_i < wr_ports; cell_port_i++)
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for (int cell_port_i = 0, bram_port_i = 0; cell_port_i < GetSize(mem.wr_ports); cell_port_i++)
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{
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bool clken = wr_clken[cell_port_i] == State::S1;
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bool clkpol = wr_clkpol[cell_port_i] == State::S1;
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SigBit clksig = wr_clk[cell_port_i];
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auto &port = mem.wr_ports[cell_port_i];
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pair<SigBit, bool> clkdom(clksig, clkpol);
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if (!clken)
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pair<SigBit, bool> clkdom(port.clk, port.clk_polarity);
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if (!port.clk_enable)
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clkdom = pair<SigBit, bool>(State::S1, false);
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wr_clkdom = clkdom;
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log(" Write port #%d is in clock domain %s%s.\n",
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cell_port_i, clkdom.second ? "" : "!",
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clken ? log_signal(clkdom.first) : "~async~");
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port.clk_enable ? log_signal(clkdom.first) : "~async~");
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for (; bram_port_i < GetSize(portinfos); bram_port_i++)
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{
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@ -609,7 +581,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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skip_bram_wport:
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continue;
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if (clken) {
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if (port.clk_enable) {
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if (pi.clocks == 0) {
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log(" Bram port %c%d has incompatible clock type.\n", pi.group + 'A', pi.index + 1);
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goto skip_bram_wport;
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@ -618,7 +590,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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log(" Bram port %c%d is in a different clock domain.\n", pi.group + 'A', pi.index + 1);
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goto skip_bram_wport;
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}
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if (clock_polarities.count(pi.clkpol) && clock_polarities.at(pi.clkpol) != clkpol) {
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if (clock_polarities.count(pi.clkpol) && clock_polarities.at(pi.clkpol) != port.clk_polarity) {
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log(" Bram port %c%d has incompatible clock polarity.\n", pi.group + 'A', pi.index + 1);
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goto skip_bram_wport;
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}
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@ -631,12 +603,12 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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SigSpec sig_en;
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SigBit last_en_bit = State::S1;
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for (int i = 0; i < mem_width; i++) {
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for (int i = 0; i < mem.width; i++) {
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if (pi.enable && i % (bram.dbits / pi.enable) == 0) {
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last_en_bit = wr_en[i + cell_port_i*mem_width];
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last_en_bit = port.en[i];
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sig_en.append(last_en_bit);
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}
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if (last_en_bit != wr_en[i + cell_port_i*mem_width]) {
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if (last_en_bit != port.en[i]) {
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log(" Bram port %c%d has incompatible enable structure.\n", pi.group + 'A', pi.index + 1);
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goto skip_bram_wport;
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}
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@ -645,7 +617,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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log(" Mapped to bram port %c%d.\n", pi.group + 'A', pi.index + 1);
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pi.mapped_port = cell_port_i;
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if (clken) {
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if (port.clk_enable) {
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clock_domains[pi.clocks] = clkdom;
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clock_polarities[pi.clkpol] = clkdom.second;
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pi.sig_clock = clkdom.first;
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@ -653,8 +625,8 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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}
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pi.sig_en = sig_en;
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pi.sig_addr = wr_addr.extract(cell_port_i*mem_abits, mem_abits);
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pi.sig_data = wr_data.extract(cell_port_i*mem_width, mem_width);
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pi.sig_addr = port.addr;
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pi.sig_data = port.data;
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bram_port_i++;
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goto mapped_wr_port;
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@ -710,23 +682,21 @@ grow_read_ports:;
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// assign read ports
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for (int cell_port_i = 0; cell_port_i < rd_ports; cell_port_i++)
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for (int cell_port_i = 0; cell_port_i < GetSize(mem.rd_ports); cell_port_i++)
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{
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bool clken = rd_clken[cell_port_i] == State::S1;
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bool clkpol = rd_clkpol[cell_port_i] == State::S1;
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bool transp = rd_transp[cell_port_i] == State::S1;
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SigBit clksig = rd_clk[cell_port_i];
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auto &port = mem.rd_ports[cell_port_i];
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bool transp = port.transparent;
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if (wr_ports == 0)
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if (mem.wr_ports.empty())
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transp = false;
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pair<SigBit, bool> clkdom(clksig, clkpol);
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if (!clken)
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pair<SigBit, bool> clkdom(port.clk, port.clk_polarity);
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if (!port.clk_enable)
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clkdom = pair<SigBit, bool>(State::S1, false);
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log(" Read port #%d is in clock domain %s%s.\n",
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cell_port_i, clkdom.second ? "" : "!",
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clken ? log_signal(clkdom.first) : "~async~");
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port.clk_enable ? log_signal(clkdom.first) : "~async~");
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for (int bram_port_i = 0; bram_port_i < GetSize(portinfos); bram_port_i++)
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{
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@ -736,7 +706,7 @@ grow_read_ports:;
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skip_bram_rport:
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continue;
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if (clken) {
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if (port.clk_enable) {
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if (pi.clocks == 0) {
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if (match.make_outreg) {
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pi.make_outreg = true;
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@ -749,20 +719,20 @@ grow_read_ports:;
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log(" Bram port %c%d.%d is in a different clock domain.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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goto skip_bram_rport;
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}
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if (clock_polarities.count(pi.clkpol) && clock_polarities.at(pi.clkpol) != clkpol) {
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if (clock_polarities.count(pi.clkpol) && clock_polarities.at(pi.clkpol) != port.clk_polarity) {
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log(" Bram port %c%d.%d has incompatible clock polarity.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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goto skip_bram_rport;
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}
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if (rd_en[cell_port_i] != State::S1 && pi.enable == 0) {
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if (port.en != State::S1 && pi.enable == 0) {
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log(" Bram port %c%d.%d has no read enable input.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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goto skip_bram_rport;
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}
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skip_bram_rport_clkcheck:
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if (read_transp.count(pi.transp) && read_transp.at(pi.transp) != transp) {
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if (match.make_transp && wr_ports <= 1) {
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if (match.make_transp && GetSize(mem.wr_ports) <= 1) {
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pi.make_transp = true;
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if (pi.clocks != 0) {
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if (wr_ports == 1 && wr_clkdom != clkdom) {
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if (GetSize(mem.wr_ports) == 1 && wr_clkdom != clkdom) {
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log(" Bram port %c%d.%d cannot have soft transparency logic added as read and write clock domains differ.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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goto skip_bram_rport;
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}
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@ -783,18 +753,18 @@ grow_read_ports:;
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log(" Mapped to bram port %c%d.%d.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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pi.mapped_port = cell_port_i;
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if (clken) {
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if (port.clk_enable) {
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clock_domains[pi.clocks] = clkdom;
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clock_polarities[pi.clkpol] = clkdom.second;
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if (!pi.make_transp)
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read_transp[pi.transp] = transp;
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pi.sig_clock = clkdom.first;
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pi.sig_en = rd_en[cell_port_i];
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pi.sig_en = port.en;
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pi.effective_clkpol = clkdom.second;
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}
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pi.sig_addr = rd_addr.extract(cell_port_i*mem_abits, mem_abits);
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pi.sig_data = rd_data.extract(cell_port_i*mem_width, mem_width);
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pi.sig_addr = port.addr;
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pi.sig_data = port.data;
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if (grow_read_ports_cursor < cell_port_i) {
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grow_read_ports_cursor = cell_port_i;
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@ -820,11 +790,11 @@ grow_read_ports:;
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match_properties["dups"] = dup_count;
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match_properties["waste"] = match_properties["dups"] * match_properties["bwaste"];
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|
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int cells = ((mem_width + bram.dbits - 1) / bram.dbits) * ((mem_size + (1 << bram.abits) - 1) / (1 << bram.abits));
|
||||
int cells = ((mem.width + bram.dbits - 1) / bram.dbits) * ((mem.size + (1 << bram.abits) - 1) / (1 << bram.abits));
|
||||
match_properties["efficiency"] = (100 * match_properties["bits"]) / (dup_count * cells * bram.dbits * (1 << bram.abits));
|
||||
|
||||
match_properties["dcells"] = ((mem_width + bram.dbits - 1) / bram.dbits);
|
||||
match_properties["acells"] = ((mem_size + (1 << bram.abits) - 1) / (1 << bram.abits));
|
||||
match_properties["dcells"] = ((mem.width + bram.dbits - 1) / bram.dbits);
|
||||
match_properties["acells"] = ((mem.size + (1 << bram.abits) - 1) / (1 << bram.abits));
|
||||
match_properties["cells"] = match_properties["dcells"] * match_properties["acells"] * match_properties["dups"];
|
||||
|
||||
log(" Updated properties: dups=%d waste=%d efficiency=%d\n",
|
||||
|
|
@ -857,8 +827,8 @@ grow_read_ports:;
|
|||
bool exists = std::get<0>(term);
|
||||
IdString key = std::get<1>(term);
|
||||
const Const &value = std::get<2>(term);
|
||||
auto it = cell->attributes.find(key);
|
||||
if (it == cell->attributes.end()) {
|
||||
auto it = mem.attributes.find(key);
|
||||
if (it == mem.attributes.end()) {
|
||||
if (exists)
|
||||
continue;
|
||||
found = true;
|
||||
|
|
@ -902,7 +872,7 @@ grow_read_ports:;
|
|||
|
||||
dict<SigSpec, pair<SigSpec, SigSpec>> dout_cache;
|
||||
|
||||
for (int grid_d = 0; grid_d*bram.dbits < mem_width; grid_d++)
|
||||
for (int grid_d = 0; grid_d*bram.dbits < mem.width; grid_d++)
|
||||
{
|
||||
SigSpec mktr_wraddr, mktr_wrdata, mktr_wrdata_q;
|
||||
vector<SigSpec> mktr_wren;
|
||||
|
|
@ -912,14 +882,14 @@ grow_read_ports:;
|
|||
mktr_wrdata = module->addWire(NEW_ID, bram.dbits);
|
||||
mktr_wrdata_q = module->addWire(NEW_ID, bram.dbits);
|
||||
module->addDff(NEW_ID, make_transp_clk.first, mktr_wrdata, mktr_wrdata_q, make_transp_clk.second);
|
||||
for (int grid_a = 0; grid_a*(1 << bram.abits) < mem_size; grid_a++)
|
||||
for (int grid_a = 0; grid_a*(1 << bram.abits) < mem.size; grid_a++)
|
||||
mktr_wren.push_back(module->addWire(NEW_ID, make_transp_enbits));
|
||||
}
|
||||
|
||||
for (int grid_a = 0; grid_a*(1 << bram.abits) < mem_size; grid_a++)
|
||||
for (int grid_a = 0; grid_a*(1 << bram.abits) < mem.size; grid_a++)
|
||||
for (int dupidx = 0; dupidx < dup_count; dupidx++)
|
||||
{
|
||||
Cell *c = module->addCell(module->uniquify(stringf("%s.%d.%d.%d", cell->name.c_str(), grid_d, grid_a, dupidx)), bram.name);
|
||||
Cell *c = module->addCell(module->uniquify(stringf("%s.%d.%d.%d", mem.memid.c_str(), grid_d, grid_a, dupidx)), bram.name);
|
||||
log(" Creating %s cell at grid position <%d %d %d>: %s\n", log_id(bram.name), grid_d, grid_a, dupidx, log_id(c));
|
||||
|
||||
for (auto &vp : variant_params)
|
||||
|
|
@ -1063,22 +1033,22 @@ grow_read_ports:;
|
|||
}
|
||||
}
|
||||
|
||||
module->remove(cell);
|
||||
mem.remove();
|
||||
return true;
|
||||
}
|
||||
|
||||
void handle_cell(Cell *cell, const rules_t &rules)
|
||||
void handle_memory(Mem &mem, const rules_t &rules)
|
||||
{
|
||||
log("Processing %s.%s:\n", log_id(cell->module), log_id(cell));
|
||||
log("Processing %s.%s:\n", log_id(mem.module), log_id(mem.memid));
|
||||
|
||||
bool cell_init = !SigSpec(cell->getParam(ID::INIT)).is_fully_undef();
|
||||
bool cell_init = !mem.inits.empty();
|
||||
|
||||
dict<string, int> match_properties;
|
||||
match_properties["words"] = cell->getParam(ID::SIZE).as_int();
|
||||
match_properties["abits"] = cell->getParam(ID::ABITS).as_int();
|
||||
match_properties["dbits"] = cell->getParam(ID::WIDTH).as_int();
|
||||
match_properties["wports"] = cell->getParam(ID::WR_PORTS).as_int();
|
||||
match_properties["rports"] = cell->getParam(ID::RD_PORTS).as_int();
|
||||
match_properties["words"] = mem.size;
|
||||
match_properties["abits"] = ceil_log2(mem.size);
|
||||
match_properties["dbits"] = mem.width;
|
||||
match_properties["wports"] = GetSize(mem.wr_ports);
|
||||
match_properties["rports"] = GetSize(mem.rd_ports);
|
||||
match_properties["bits"] = match_properties["words"] * match_properties["dbits"];
|
||||
match_properties["ports"] = match_properties["wports"] + match_properties["rports"];
|
||||
|
||||
|
|
@ -1181,8 +1151,8 @@ void handle_cell(Cell *cell, const rules_t &rules)
|
|||
bool exists = std::get<0>(term);
|
||||
IdString key = std::get<1>(term);
|
||||
const Const &value = std::get<2>(term);
|
||||
auto it = cell->attributes.find(key);
|
||||
if (it == cell->attributes.end()) {
|
||||
auto it = mem.attributes.find(key);
|
||||
if (it == mem.attributes.end()) {
|
||||
if (exists)
|
||||
continue;
|
||||
found = true;
|
||||
|
|
@ -1219,7 +1189,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
|
|||
if (or_next_if_better && i+1 == GetSize(rules.matches) && vi+1 == GetSize(rules.brams.at(match.name)))
|
||||
log_error("Found 'or_next_if_better' in last match rule.\n");
|
||||
|
||||
if (!replace_cell(cell, rules, bram, match, match_properties, 1)) {
|
||||
if (!replace_memory(mem, rules, bram, match, match_properties, 1)) {
|
||||
log(" Mapping to bram type %s failed.\n", log_id(match.name));
|
||||
failed_brams.insert(pair<IdString, int>(bram.name, bram.variant));
|
||||
goto next_match_rule;
|
||||
|
|
@ -1246,12 +1216,12 @@ void handle_cell(Cell *cell, const rules_t &rules)
|
|||
best_rule_cache.clear();
|
||||
|
||||
auto &best_bram = rules.brams.at(rules.matches.at(best_rule.first).name).at(best_rule.second);
|
||||
if (!replace_cell(cell, rules, best_bram, rules.matches.at(best_rule.first), match_properties, 2))
|
||||
if (!replace_memory(mem, rules, best_bram, rules.matches.at(best_rule.first), match_properties, 2))
|
||||
log_error("Mapping to bram type %s (variant %d) after pre-selection failed.\n", log_id(best_bram.name), best_bram.variant);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!replace_cell(cell, rules, bram, match, match_properties, 0)) {
|
||||
if (!replace_memory(mem, rules, bram, match, match_properties, 0)) {
|
||||
log(" Mapping to bram type %s failed.\n", log_id(match.name));
|
||||
failed_brams.insert(pair<IdString, int>(bram.name, bram.variant));
|
||||
goto next_match_rule;
|
||||
|
|
@ -1384,9 +1354,8 @@ struct MemoryBramPass : public Pass {
|
|||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto mod : design->selected_modules())
|
||||
for (auto cell : mod->selected_cells())
|
||||
if (cell->type == ID($mem))
|
||||
handle_cell(cell, rules);
|
||||
for (auto &mem : Mem::get_selected_memories(mod))
|
||||
handle_memory(mem, rules);
|
||||
}
|
||||
} MemoryBramPass;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue