mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

sim -vcd: add date, version, and option for timescale

Browse source
This commit is contained in:
N. Engelhardt 2020-10-16 18:19:58 +02:00
parent 4c925a3214
commit 668d5253a5
1 changed files with 17 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

17
passes/sat/sim.cc
View file

@ -633,6 +633,7 @@ struct SimWorker : SimShared
SimInstance *top = nullptr;
std::ofstream vcdfile;
pool<IdString> clock, clockn, reset, resetn;
std::string timescale;
~SimWorker()
{
@ -644,6 +645,15 @@ struct SimWorker : SimShared
if (!vcdfile.is_open())
return;
vcdfile << stringf("$version %s $end\n", yosys_version_str);
vcdfile << stringf("$date ");
std::time_t t = std::time(nullptr);
vcdfile << std::put_time(std::localtime(&t), "%c %Z");
vcdfile << stringf(" $end\n");
if (!timescale.empty())
vcdfile << stringf("$timescale %s $end\n", timescale.c_str());
int id = 1;
top->write_vcd_header(vcdfile, id);
@ -783,6 +793,9 @@ struct SimPass : public Pass {
log(" -zinit\n");
log(" zero-initialize all uninitialized regs and memories\n");
log("\n");
log(" -timescale <string>\n");
log(" include the specified timescale declaration in the vcd\n");
log("\n");
log(" -n <integer>\n");
log(" number of cycles to simulate (default: 20)\n");
log("\n");
@ -833,6 +846,10 @@ struct SimPass : public Pass {
worker.resetn.insert(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-timescale" && argidx+1 < args.size()) {
worker.timescale = args[++argidx];
continue;
}
if (args[argidx] == "-a") {
worker.hide_internal = false;
continue;