mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity
15391 commits 122 branches 59 tags 73 MiB
Commit graph

34 commits

Author SHA1 Message Date
Akash Levy
2ae7490adf Disable Verific blackbox checks (different from our preferred approach) 2025-01-21 05:46:40 -08:00
Akash Levy
53ed83fcac Rename verific to import in tests and update README explanation 2025-01-16 19:34:02 -08:00
Akash Levy
1dcf75d175 Sync 2024-12-19 21:40:30 -08:00
Emil J
6ab5be4a0e
Merge pull request #4814 from YosysHQ/emil/make-test-fasterer 
test: every test everywhere all at once
 2024-12-18 19:02:39 +01:00
Emil J. Tywoniak
6240aec433 test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
Akash Levy
1242db626f Merge remote-tracking branch 'upstream/main' 2024-12-12 22:49:19 -08:00
N. Engelhardt
378864d33b bound attributes: handle vhdl null ranges 2024-12-12 11:42:39 +01:00
N. Engelhardt
03033ab6d4 add more tests for bounds attributes, fix attributes appearing in verilog 2024-12-11 16:11:02 +01:00
Akash Levy
e0ba08dd1d
Merge branch 'YosysHQ:main' into main 2024-12-09 11:13:47 -08:00
Akash Levy
8bb193d7c5
Merge branch 'YosysHQ:main' into main 2024-12-08 15:44:46 -08:00
Miodrag Milanovic
05398889ad Add verific verilog test cases for blackboxes 2024-12-06 16:13:25 +01:00
N. Engelhardt
8b0f665cc5 add setenv pass 2024-12-06 11:25:43 +01:00
Akash Levy
3914c21286 verific->import fix for new test case 2024-12-02 20:07:07 -05:00
Akash Levy
6e88c689f2
Merge branch 'YosysHQ:main' into main 2024-12-01 12:32:07 -05:00
Miodrag Milanovic
df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
Akash Levy
2d8588f15b Update Verific 2024-10-02 23:09:36 -07:00
Akash Levy
ed2c65314b Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
Akash Levy
138228d96e Update Verific README 2024-09-23 05:35:48 -07:00
Akash Levy
0fd6e29e8e Fixups 2024-09-23 04:25:10 -07:00
Akash Levy
2d771a352e Clean up Verific tests 2024-09-23 04:05:08 -07:00
Akash Levy
2c3d2b3ec6 Clocking works with -formal flag 2024-09-22 08:01:16 -07:00
Akash Levy
69bf7875dd Small edits 2024-09-22 07:52:58 -07:00
Akash Levy
285c8a3f66
Merge branch 'YosysHQ:main' into main 2024-09-12 11:14:15 -07:00
Roland Coeurjoly
bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
Akash Levy
29e9d3ea92 Updates for hiding verific 2024-04-09 07:16:22 -07:00
Akash Levy
dd35d2da23 Modifications 2024-03-21 11:31:43 -07:00
Miodrag Milanovic
d00843d436 Add -nordff to test 2024-02-06 10:36:30 +01:00
Miodrag Milanovic
1764c0ee3c Fix verific clocking when no driver exist 2024-01-18 08:47:04 +01:00
N. Engelhardt
833b67af80 verific: import attributes on ports 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
 2023-10-20 18:31:41 +02:00
N. Engelhardt
1b6d1e9419 memory_libmap: look for ram_style attributes on surrounding signals 2023-10-19 19:23:35 +02:00
Martin Povišer
8222121164 verific: Add test of accurate semantics in memory inference 2023-09-18 16:37:15 +02:00
Jannis Harder
390d1c583a verific: Fix enum_values support and signed attribute values 
This uses the same constant parsing for enum_values and for attributes
and extends it to handle signed values as those are used for enums that
implicitly use the int type.
 2023-03-15 09:51:36 +01:00
Miodrag Milanovic
d8cefec169 Added ranged case check 2023-02-27 09:24:04 +01:00
Miodrag Milanovic
53a4f0fb56 Add test example 2023-02-27 09:24:04 +01:00