1257 commits

Author	SHA1	Message	Date
Eddie Hung	449b1d2c6f	Add comment, use sigmap	2019-11-27 13:20:12 -08:00
Eddie Hung	403214f44d	Revert "Fold loop" ... This reverts commit da51492dbc.	2019-11-27 12:35:25 -08:00
Eddie Hung	5e67df38ed	latch -> box	2019-11-26 22:59:05 -08:00
Eddie Hung	a30d5e1cc3	Fold loop	2019-11-26 21:57:50 -08:00
Eddie Hung	68717dd03b	Do not sigmap keep bits inside write_xaiger	2019-11-26 21:57:50 -08:00
Eddie Hung	7136cee6b4	xaiger: do not promote output wires	2019-11-26 21:55:37 -08:00
Eddie Hung	99702efaba	xaiger: do not promote output wires	2019-11-26 19:03:02 -08:00
Eddie Hung	da51492dbc	Fold loop	2019-11-25 15:43:37 -08:00
Eddie Hung	7f0914a408	Do not sigmap keep bits inside write_xaiger	2019-11-25 15:42:07 -08:00
Eddie Hung	81548d1ef9	write_xaiger back to working with whole modules only	2019-11-22 16:52:17 -08:00
Eddie Hung	8ef241c6f4	Revert "write_xaiger to not use module POs but only write outputs if driven" ... This reverts commit 0ab1e496dc.	2019-11-22 13:24:28 -08:00
Eddie Hung	0ab1e496dc	write_xaiger to not use module POs but only write outputs if driven	2019-11-21 16:19:28 -08:00
Eddie Hung	929beda19c	abc9 to support async flops $_DFF_[NP][NP][01]_	2019-11-19 16:57:26 -08:00
Eddie Hung	09ee96e8c2	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-11-19 15:40:39 -08:00
whitequark	3c643c57df	write_verilog: add -extmem option, to write split memory init files. ... Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used.	2019-11-18 01:27:21 +00:00
Clifford Wolf	cd44826d50	Use cell name for btor bad state props when it is a public name ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-11-14 11:57:38 +01:00
Makai Mann	d88cc139a0	Add an info string symbol for bad states in btor backend	2019-11-11 16:40:51 -08:00
Clifford Wolf	5110a34dd7	Fix write_aiger bug added in 524af21 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-11-04 14:25:13 +01:00
Clifford Wolf	81876a3734	Merge pull request #1393 from whitequark/write_verilog-avoid-init ... write_verilog: do not print (*init*) attributes on regs	2019-10-27 10:25:01 +01:00
Clifford Wolf	f02623abb5	Bugfix in smtio vcd handling of $-identifiers ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-10-23 00:04:34 +02:00
Eddie Hung	b2e34f932a	Rename $currQ to $abc9_currQ	2019-10-07 15:31:43 -07:00
Eddie Hung	90a954bb9c	Get rid of latch_* in write_xaiger	2019-10-07 13:09:13 -07:00
Eddie Hung	1504ca2cd9	Remove "write_xaiger -zinit"	2019-10-07 11:58:49 -07:00
Eddie Hung	e1554b56dd	Add comment on default flop init	2019-10-07 11:56:17 -07:00
Eddie Hung	d9fba95177	Get rid of output_port lookup	2019-10-07 11:49:06 -07:00
Eddie Hung	3879ca1398	Do not require changes to cells_sim.v; try and work out comb model	2019-10-05 22:55:18 -07:00
Eddie Hung	3c6e5d82a6	Error if $currQ not found	2019-10-05 09:06:13 -07:00
Eddie Hung	7959e9d6b2	Fix merge issues	2019-10-04 17:21:14 -07:00
Eddie Hung	7a45cd5856	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	2019-10-04 16:58:55 -07:00
Eddie Hung	aae2b9fd9c	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00
Eddie Hung	549d6ea467	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-10-03 10:55:23 -07:00
Clifford Wolf	2ed2e9c3e8	Change smtbmc "Warmup failed" status to "PREUNSAT" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-10-03 14:59:07 +02:00
Clifford Wolf	a84a2d74c7	Fix btor back-end to use "state" instead of "input" for undef init bits ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-10-02 12:48:04 +02:00
Eddie Hung	1b96d29174	No need to punch ports at all	2019-09-30 17:02:20 -07:00
Eddie Hung	e529872b01	Remove need for $currQ port connection	2019-09-30 16:33:40 -07:00
Eddie Hung	eecfdda614	Cleanup	2019-09-30 15:24:03 -07:00
Eddie Hung	74678227c7	Use a cell_cache to instantiate once rather than opt_merge call	2019-09-30 13:21:07 -07:00
Eddie Hung	a6994c5f16	scc call on active module module only, plus cleanup	2019-09-30 12:57:19 -07:00
Eddie Hung	bd8356799a	Use derived module	2019-09-30 12:34:28 -07:00
Eddie Hung	1123c09588	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-29 19:39:12 -07:00
Eddie Hung	8474c5b366	Merge pull request #1359 from YosysHQ/xc7dsp ... DSP inference for Xilinx (improved for ice40, initial support for ecp5)	2019-09-29 11:26:22 -07:00
Eddie Hung	f3e150d9a5	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-29 09:21:51 -07:00
Miodrag Milanović	ce0631c371	Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out ... Support binary files for backends, fixes #1407	2019-09-29 10:37:34 +02:00
Eddie Hung	79b6edb639	Big rework; flop info now mostly in cells_sim.v	2019-09-28 23:48:17 -07:00
Miodrag Milanovic	0c380f0855	Add aiger and protobuf backends binary support	2019-09-28 09:51:48 +02:00
Miodrag Milanovic	d0493925ec	Support binary files for backends, fixes #1407	2019-09-28 09:36:18 +02:00
Eddie Hung	cfa6dd61ef	Use abc_mergeability attr for "r" extension	2019-09-27 18:41:43 -07:00
Eddie Hung	dc154c39a8	Fix infinite recursion	2019-09-27 17:45:49 -07:00
Eddie Hung	8f5710c464	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-27 15:14:31 -07:00
Aman Goel	5eebfabe42	Corrects btor2 backend	2019-09-27 12:40:17 -04:00