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xaiger: do not promote output wires
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1 changed files with 0 additions and 5 deletions
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@ -155,11 +155,6 @@ struct XAigerWriter
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if (wire->port_input)
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sigmap.add(wire);
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// promote output wires
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for (auto wire : module->wires())
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if (wire->port_output)
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sigmap.add(wire);
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for (auto wire : module->wires())
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{
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if (wire->attributes.count("\\init")) {
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