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									 Clifford Wolf | dfcd30ea86 | Added printing of code loc of failed asserts to yosys-smtbmc | 2016-08-17 20:10:02 +02:00 |  | 
				
					
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									 Clifford Wolf | f0a8713fea | Fixed upto handling in verilog back-end | 2016-08-15 08:26:20 +02:00 |  | 
				
					
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									 Clifford Wolf | 21e1bac084 | Merge branch 'master' of github.com:cliffordwolf/yosys | 2016-07-30 12:50:39 +02:00 |  | 
				
					
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									 Clifford Wolf | 5fe13a16ea | Added "write_verilog -defparam" | 2016-07-30 12:46:06 +02:00 |  | 
				
					
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									 Clifford Wolf | 7fa61cba1b | Added "write_verilog -nodec -nostr" | 2016-07-30 12:38:40 +02:00 |  | 
				
					
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									 Clifford Wolf | da56a5bbc6 | Added $initstate support to smtbmc flow | 2016-07-27 16:11:37 +02:00 |  | 
				
					
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									 whitequark | 546233f0e1 | write_json: also write module attributes. | 2016-07-12 06:32:04 +00:00 |  | 
				
					
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									 Clifford Wolf | c71785d65e | Yosys-smtbmc: Support for hierarchical VCD dumping | 2016-07-11 12:49:33 +02:00 |  | 
				
					
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									 Clifford Wolf | 0153ad85d9 | Moved smt2 yosys info parsing from smtbmc.py to smtio.py | 2016-07-11 11:49:05 +02:00 |  | 
				
					
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									 Clifford Wolf | 771c5fe000 | Support for hierarchical designs in smt2 back-end | 2016-07-10 18:11:25 +02:00 |  | 
				
					
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									 Clifford Wolf | 27b5347a87 | Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior | 2016-07-08 11:51:04 +02:00 |  | 
				
					
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									 Clifford Wolf | 72149aba2e | In BLIF, a .names without entries already always outputs 0 | 2016-07-08 11:41:26 +02:00 |  | 
				
					
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									 Clifford Wolf | f6b7cf23d6 | Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into eddiehung-vtr | 2016-07-08 11:32:36 +02:00 |  | 
				
					
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									 Clifford Wolf | 5ffad4e073 | Added $sop support to BLIF back-end | 2016-06-18 12:28:49 +02:00 |  | 
				
					
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									 Clifford Wolf | f3983a0940 | Also escape "=" in spice output | 2016-05-20 16:43:13 +02:00 |  | 
				
					
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									 Clifford Wolf | d10dfccabb | Added "write_blif -noalias" | 2016-05-06 15:05:53 +02:00 |  | 
				
					
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									 Clifford Wolf | 60ac1bd178 | Added support for "active high" and "active low" latches in BLIF back-end | 2016-04-22 18:00:46 +02:00 |  | 
				
					
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									 Clifford Wolf | 0bc95f1e04 | Added "yosys -D" feature | 2016-04-21 23:28:37 +02:00 |  | 
				
					
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									 Clifford Wolf | 3920bf58d0 | Fixed some typos | 2016-04-05 08:18:21 +02:00 |  | 
				
					
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									 Clifford Wolf | 1d0f0d668a | Renamed opt_const to opt_expr | 2016-03-31 08:46:56 +02:00 |  | 
				
					
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									 Clifford Wolf | 2a8d5e64f5 | Bugfix in write_verilog for RTLIL processes | 2016-03-14 13:03:28 +01:00 |  | 
				
					
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									 Clifford Wolf | d117893007 | Added "write_edif -nogndvcc" | 2016-03-08 21:30:45 +01:00 |  | 
				
					
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									 Clifford Wolf | 5547fae4cf | Be more conservative with net names in spice output | 2016-03-02 12:02:59 +01:00 |  | 
				
					
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									 Sebastian Kuzminsky | 7e6426a67d | user-facing spelling fixes "speciefied" -> "specified"
"unkown" -> "unknown" | 2016-02-28 15:14:01 -07:00 |  | 
				
					
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									 Clifford Wolf | 0d7fd2585e | Added "int ceil_log2(int)" function | 2016-02-13 16:52:16 +01:00 |  | 
				
					
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									 Clifford Wolf | 4393a8ffbf | Added "write_blif -cname" mode | 2016-01-06 14:32:28 +01:00 |  | 
				
					
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									 Clifford Wolf | 47fac573cf | Added yosys-smtbmc -S | 2015-12-20 09:58:54 +01:00 |  | 
				
					
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									 Clifford Wolf | 207736b4ee | Import more std:: stuff into Yosys namespace | 2015-10-25 19:30:49 +01:00 |  | 
				
					
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									 Clifford Wolf | 7f110e7018 | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() | 2015-10-24 22:56:40 +02:00 |  | 
				
					
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									 Clifford Wolf | 255bb914ba | Progress in yosys-smtbmc | 2015-10-15 15:54:59 +02:00 |  | 
				
					
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									 Clifford Wolf | 302166dd59 | Improvements in yosys-smtbmc | 2015-10-15 15:10:33 +02:00 |  | 
				
					
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									 Clifford Wolf | 5dd3e93e8f | More "yosys-smtbmc -c" fixes | 2015-10-14 23:23:25 +02:00 |  | 
				
					
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									 Clifford Wolf | 9fd0f87059 | Fixed yosys-smtbmc -c | 2015-10-14 23:00:46 +02:00 |  | 
				
					
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									 Clifford Wolf | 3c31572152 | Added yosys-smtbmc copyright | 2015-10-14 01:31:54 +02:00 |  | 
				
					
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									 Clifford Wolf | d7de0f4bd1 | Improvements in yosys-smtbmc | 2015-10-14 01:27:55 +02:00 |  | 
				
					
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									 Clifford Wolf | 821f1b8534 | Added yosys-smtbmc | 2015-10-14 00:47:04 +02:00 |  | 
				
					
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									 Clifford Wolf | 7bcd2a4bb3 | Implemented smtbmc.py -i | 2015-10-14 00:18:38 +02:00 |  | 
				
					
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									 Clifford Wolf | 29160525aa | Added smtbmc.py | 2015-10-13 17:17:23 +02:00 |  | 
				
					
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									 Clifford Wolf | 3a22b31bda | Added write_smt2 -wires | 2015-10-13 17:17:12 +02:00 |  | 
				
					
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									 Clifford Wolf | 4ac202e2a5 | Bugfixes in writing of memories as Verilog | 2015-09-25 13:49:26 +02:00 |  | 
				
					
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									 Clifford Wolf | 09b51cb375 | Added "yosys-smt2-wire" tag support to smt2 back-end | 2015-08-31 02:05:58 +02:00 |  | 
				
					
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									 Clifford Wolf | b659ffb457 | Fixed generation of smt2 concat statements | 2015-08-15 11:45:44 +02:00 |  | 
				
					
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									 Larry Doolittle | 6c00704a5e | Another block of spelling fixes Smaller this time | 2015-08-14 23:27:05 +02:00 |  | 
				
					
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									 Clifford Wolf | 0350074819 | Re-created command-reference-manual.tex, copied some doc fixes to online help | 2015-08-14 11:27:19 +02:00 |  | 
				
					
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									 Clifford Wolf | 84bf862f7c | Spell check (by Larry Doolittle) | 2015-08-14 10:56:05 +02:00 |  | 
				
					
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									 Clifford Wolf | 698357dd9a | Added "write_smt2 -regs" | 2015-08-12 17:13:54 +02:00 |  | 
				
					
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									 Clifford Wolf | f81bf9bdea | Added SMV back-end 'test_cells.sh' script | 2015-08-12 12:56:20 +02:00 |  | 
				
					
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									 Clifford Wolf | 883e09d8ed | Use MEMID as name for $mem cell | 2015-08-09 13:35:44 +02:00 |  | 
				
					
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									 Clifford Wolf | 6834461f65 | Remove some very strange whitespace in btor.cc (by Larry Doolittle) | 2015-08-05 22:11:26 +02:00 |  | 
				
					
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									 Clifford Wolf | 5dc23975eb | Bugfix in SMV back-end for partially unassigned wires | 2015-08-05 11:36:26 +02:00 |  |