mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

Added "yosys -D" feature

Browse source
This commit is contained in:
Clifford Wolf 2016-04-21 23:28:37 +02:00
parent 1565d1af69
commit 0bc95f1e04
113 changed files with 172 additions and 145 deletions
Download patch file Download diff file Expand all files Collapse all files

2
backends/blif/blif.cc
View file

@ -448,7 +448,7 @@ struct BlifBackend : public Backend {
std::string false_type, false_out;
BlifDumperConfig config;
log_header("Executing BLIF backend.\n");
log_header(design, "Executing BLIF backend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
backends/btor/btor.cc
View file

@ -1065,7 +1065,7 @@ struct BtorBackend : public Backend {
std::string false_type, false_out;
BtorDumperConfig config;
log_header("Executing BTOR backend.\n");
log_header(design, "Executing BTOR backend.\n");
size_t argidx=1;
extra_args(f, filename, args, argidx);

2
backends/edif/edif.cc
View file

@ -113,7 +113,7 @@ struct EdifBackend : public Backend {
}
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing EDIF backend.\n");
log_header(design, "Executing EDIF backend.\n");
std::string top_module_name;
std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;

2
backends/ilang/ilang_backend.cc
View file

@ -391,7 +391,7 @@ struct IlangBackend : public Backend {
{
bool selected = false;
log_header("Executing ILANG backend.\n");
log_header(design, "Executing ILANG backend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

4
backends/intersynth/intersynth.cc
View file

@ -73,7 +73,7 @@ struct IntersynthBackend : public Backend {
}
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing INTERSYNTH backend.\n");
log_header(design, "Executing INTERSYNTH backend.\n");
log_push();
std::vector<std::string> libfiles;
@ -113,7 +113,7 @@ struct IntersynthBackend : public Backend {
}
if (libs.size() > 0)
log_header("Continuing INTERSYNTH backend.\n");
log_header(design, "Continuing INTERSYNTH backend.\n");
std::set<std::string> conntypes_code, celltypes_code;
std::string netlists_code;

2
backends/json/json.cc
View file

@ -463,7 +463,7 @@ struct JsonBackend : public Backend {
}
extra_args(f, filename, args, argidx);
log_header("Executing JSON backend.\n");
log_header(design, "Executing JSON backend.\n");
JsonWriter json_writer(*f, false, aig_mode);
json_writer.write_design(design);

2
backends/smt2/smt2.cc
View file

@ -758,7 +758,7 @@ struct Smt2Backend : public Backend {
std::ifstream template_f;
bool bvmode = false, memmode = false, regsmode = false, wiresmode = false, verbose = false;
log_header("Executing SMT2 backend.\n");
log_header(design, "Executing SMT2 backend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
backends/smv/smv.cc
View file

@ -694,7 +694,7 @@ struct SmvBackend : public Backend {
std::ifstream template_f;
bool verbose = false;
log_header("Executing SMV backend.\n");
log_header(design, "Executing SMV backend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
backends/spice/spice.cc
View file

@ -168,7 +168,7 @@ struct SpiceBackend : public Backend {
bool big_endian = false, use_inames = false;
std::string neg = "Vss", pos = "Vdd", ncpf = "_NC";
log_header("Executing SPICE backend.\n");
log_header(design, "Executing SPICE backend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
backends/verilog/verilog_backend.cc
View file

@ -1363,7 +1363,7 @@ struct VerilogBackend : public Backend {
}
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing Verilog backend.\n");
log_header(design, "Executing Verilog backend.\n");
norename = false;
noattr = false;