Spell check (by Larry Doolittle)

backends/btor/btor.cc

@@ -70,7 +70,7 @@ struct BtorDumper
 	CellTypes ct;
 
 	SigMap sigmap;
-	std::map<RTLIL::IdString, std::set<WireInfo,WireInfoOrder>> inter_wire_map;//<wire, dependency list> for maping the intermediate wires that are output of some cell
+	std::map<RTLIL::IdString, std::set<WireInfo,WireInfoOrder>> inter_wire_map;//<wire, dependency list> for mapping the intermediate wires that are output of some cell
 	std::map<RTLIL::IdString, int> line_ref;//mapping of ids to line_num of the btor file
 	std::map<RTLIL::SigSpec, int> sig_ref;//mapping of sigspec to the line_num of the btor file
 	int line_num;//last line number of btor file
@@ -722,7 +722,7 @@ struct BtorDumper
             //registers
 			else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
 			{
-				//TODO: remodelling fo adff cells
+				//TODO: remodelling of adff cells
 				log("writing cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				log(" - width is %d\n", output_width);

backends/verilog/verilog_backend.cc

@@ -284,7 +284,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 		f << stringf("[%d:%d] ", wire->width - 1 + wire->start_offset, wire->start_offset);
 	f << stringf("%s;\n", id(wire->name).c_str());
 #else
-	// do not use Verilog-2k "outut reg" syntax in verilog export
+	// do not use Verilog-2k "output reg" syntax in Verilog export
 	std::string range = "";
 	if (wire->width != 1) {
 		if (wire->upto)