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Fixed upto handling in verilog back-end

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This commit is contained in:
Clifford Wolf 2016-08-15 08:26:20 +02:00
parent 1058660ac8
commit f0a8713fea
1 changed files with 3 additions and 0 deletions
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backends/verilog/verilog_backend.cc
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@ -141,6 +141,9 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
if (sig.size() != chunk.wire->width) {
if (sig.size() == 1)
reg_name += stringf("[%d]", chunk.wire->start_offset + chunk.offset);
else if (chunk.wire->upto)
reg_name += stringf("[%d:%d]", (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset,
(chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset);
else
reg_name += stringf("[%d:%d]", chunk.wire->start_offset + chunk.offset + chunk.width - 1,
chunk.wire->start_offset + chunk.offset);