488 commits

Author	SHA1	Message	Date
Eddie Hung	5d0f6cbd54	techmap before read	2019-08-21 11:47:06 -07:00
Eddie Hung	584c680691	Add abc_arrival to SRL*	2019-08-21 11:27:42 -07:00
Eddie Hung	64d62710de	Oops	2019-08-20 20:07:38 -07:00
Eddie Hung	c26c556384	xilinx to use abc_map.v with -max_iter 1	2019-08-20 19:47:11 -07:00
Eddie Hung	343039496b	Add reference to FD* timing	2019-08-20 18:22:58 -07:00
Eddie Hung	091bf4a18b	Remove sequential extension	2019-08-20 18:16:37 -07:00
Eddie Hung	bbab608691	Remove SRL* delays from cells_sim.v	2019-08-20 18:14:40 -07:00
Eddie Hung	aa2d3af631	LUTMUX -> LUTMUX6	2019-08-20 18:08:07 -07:00
Eddie Hung	30a379b5b6	Cleanup techmap in map_luts	2019-08-20 17:59:31 -07:00
Eddie Hung	3b52d6e29c	Move techmap abc_map.v into map_luts	2019-08-20 17:55:12 -07:00
Eddie Hung	54284aaa98	Remove delays from abc_map.v	2019-08-20 17:52:27 -07:00
Eddie Hung	96f00e9147	Typo	2019-08-20 17:51:50 -07:00
Eddie Hung	8f666ebac1	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-08-20 17:36:14 -07:00
Eddie Hung	e273ed5275	Wrap SRL{16,32} too	2019-08-20 15:09:38 -07:00
Eddie Hung	808f07630f	Wrap LUTRAMs in order to capture comb/seq behaviour	2019-08-20 14:49:11 -07:00
Eddie Hung	0079e9b4a6	Add LUTRAM delays	2019-08-20 13:53:38 -07:00
Eddie Hung	8d0cffaf20	Remove mapping rules	2019-08-20 13:11:39 -07:00
Eddie Hung	33960dd3d8	Merge pull request #1209 from YosysHQ/eddie/synth_xilinx ... [WIP] synth xilinx renaming, as per #1184	2019-08-20 12:55:26 -07:00
Eddie Hung	5eda5fc7eb	Remove -icells	2019-08-20 12:41:11 -07:00
Eddie Hung	be9e4f1b67	Use abc_{map,unmap,model}.v	2019-08-20 12:39:11 -07:00
Eddie Hung	c4d4c6db3f	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-08-20 12:00:12 -07:00
Eddie Hung	d9fe4cccbf	Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx	2019-08-20 11:57:52 -07:00
Eddie Hung	526e081342	Add arrival times for SRL outputs	2019-08-19 15:15:43 -07:00
Eddie Hung	b71212ddea	Add BRAM arrival times	2019-08-19 12:46:35 -07:00
Eddie Hung	2f86366087	Add reference to source of Tclktoq timing	2019-08-19 12:39:22 -07:00
Eddie Hung	d02ef8c73f	Add 'abc_arrival' attribute for flop outputs	2019-08-19 11:32:18 -07:00
Eddie Hung	f25837f8e8	Update box timings	2019-08-19 11:31:40 -07:00
Eddie Hung	ba2261e21a	Move from cell attr to module attr	2019-08-19 11:18:33 -07:00
Eddie Hung	d81a090d89	Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro	2019-08-19 09:56:17 -07:00
Eddie Hung	e301440a0b	Use attributes instead of params	2019-08-19 09:51:49 -07:00
Eddie Hung	24c934f1af	Merge branch 'eddie/abc9_refactor' into xaig_dff	2019-08-16 16:51:22 -07:00
Eddie Hung	562c9e3624	Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules	2019-08-16 15:40:53 -07:00
Eddie Hung	48d0f99406	stoi -> atoi	2019-08-07 11:09:17 -07:00
Eddie Hung	66806085db	RST -> RSTBRST for RAMB8BWER	2019-07-29 16:05:44 -07:00
David Shah	ab607e896e	xilinx: Fix missing cell name underscore in cells_map.v ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-25 08:19:07 +01:00
Eddie Hung	43616e1414	Update Makefile too	2019-07-18 14:51:55 -07:00
Eddie Hung	b97fe6e866	Work in progress for renaming labels/options in synth_xilinx	2019-07-18 14:20:43 -07:00
Eddie Hung	1c9f3fadb9	Add Tsu offset to boxes, and comments	2019-07-11 17:17:26 -07:00
Eddie Hung	d386177e6d	ABC doesn't like negative delays in flop boxes...	2019-07-11 17:09:17 -07:00
Eddie Hung	3ef927647c	Fix FDCE_1 box	2019-07-11 14:25:47 -07:00
Eddie Hung	1ada568134	Revert "$pastQ should be first input" ... This reverts commit 8f9d529929.	2019-07-11 14:23:45 -07:00
Eddie Hung	854333f2af	Propagate INIT attr	2019-07-11 13:55:47 -07:00
Eddie Hung	8f9d529929	$pastQ should be first input	2019-07-11 13:54:40 -07:00
Eddie Hung	021f8e5492	Fix typo	2019-07-11 13:23:07 -07:00
Eddie Hung	19c1c3cfa3	Merge pull request #1182 from koriakin/xc6s-bram ... synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 12:55:35 -07:00
Marcin Kościelnicki	a9efacd01d	xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 21:13:12 +02:00
Eddie Hung	8fef4c3594	Simplify to $__ABC_ASYNC box	2019-07-11 10:52:33 -07:00
Eddie Hung	93fbd56db1	$__ABC_FD_ASYNC_MUX.Q -> Y	2019-07-11 10:25:59 -07:00
Marcin Kościelnicki	ce250b341c	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
Eddie Hung	d357431df1	Restore from master	2019-07-10 22:54:39 -07:00