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4252 commits 98 branches 53 tags 45 MiB
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1352 commits

Author SHA1 Message Date
whitequark
4fd458290c opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI. 2019-01-02 05:11:29 +00:00
whitequark
9e9846a6ea opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. 2019-01-02 03:01:25 +00:00
whitequark
8e53d2e0bf opt_expr: simplify any unsigned comparisons with all-0 and all-1. 
Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
 2019-01-02 02:45:49 +00:00
whitequark
42c356c49c opt_lut: eliminate LUTs evaluating to constants or inputs. 2018-12-31 23:55:40 +00:00
Clifford Wolf
0a840dd883 Fix handling of (* keep *) wires in wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-31 16:37:40 +01:00
whitequark
18291c20d2 proc_clean: remove any empty cases if all cases use all-def compare. 2018-12-23 09:04:30 +00:00
whitequark
b784440857 proc_clean: remove any empty cases at the end of the switch. 
Previously, only completely empty switches were removed.
 2018-12-22 09:04:46 +00:00
whitequark
0c318e7db5 memory_collect: do not truncate 'x from \INIT. 
The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
 2018-12-21 02:01:27 +00:00
David Shah
2b16d4ed3d memory_dff: Fix typo when checking init value 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-18 17:40:01 +00:00
Clifford Wolf
2641a3089b
Revert "Proof-of-concept: preserve naming through ABC using dress" 2018-12-16 21:27:31 +01:00
Clifford Wolf
ddff75b60a
Merge pull request from whitequark/select_assert_list 
select: print selection if a -assert-* flag causes an error
 2018-12-16 16:45:49 +01:00
whitequark
f6412d7109 select: print selection if a -assert-* flag causes an error. 2018-12-16 15:44:29 +00:00
Clifford Wolf
0d9c850a07
Merge pull request from daveshah1/trifixes 
deminout fixes
 2018-12-16 16:02:21 +01:00
Clifford Wolf
f53e19cc71 Fix equiv_opt indenting 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-16 15:57:28 +01:00
Clifford Wolf
2a681909df
Merge pull request from whitequark/equiv_opt 
equiv_opt: new command, for verifying optimization passes
 2018-12-16 15:54:26 +01:00
Clifford Wolf
a2154c1be0
Merge pull request from grahamedgecombe/fix-shuffled-bram-initdata 
memory_bram: Fix initdata bit order after shuffling
 2018-12-16 15:53:44 +01:00
Clifford Wolf
a1fb5b1e4b
Merge pull request from daveshah1/abc_preserve_naming 
Proof-of-concept: preserve naming through ABC using dress
 2018-12-16 15:41:30 +01:00
Clifford Wolf
19ca4e2ac3
Merge pull request from whitequark/rename_src 
rename: add -src, for inferring names from source locations
 2018-12-16 15:28:29 +01:00
Clifford Wolf
556341a77f
Merge pull request from whitequark/master 
lut2mux: handle 1-bit INIT constant in $lut cells
 2018-12-16 15:27:23 +01:00
David Shah
4c59447168 deminout: Consider $tribuf cells 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-12 17:17:40 +00:00
David Shah
d3fe9465f3 deminout: Don't demote constant-driven inouts to inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-12 16:50:46 +00:00
Graham Edgecombe
4fef9689ab memory_bram: Fix initdata bit order after shuffling 
In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.

This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).

This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
 2018-12-11 21:02:49 +00:00
whitequark
7ff5a9db2d equiv_opt: pass -D EQUIV when techmapping. 
This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
 2018-12-07 17:20:34 +00:00
whitequark
c38ea9ae65 equiv_opt: new command, for verifying optimization passes. 2018-12-07 17:20:34 +00:00
whitequark
7ec740b7ad opt_lut: leave intact LUTs with cascade feeding module outputs. 2018-12-07 17:13:52 +00:00
whitequark
9eb03d458d opt_lut: show original truth table for both cells. 2018-12-07 17:04:41 +00:00
whitequark
a8ab722824 opt_lut: add -limit option, for debugging misoptimizations. 2018-12-07 16:36:26 +00:00
David Shah
1dfb2fecab abc: Preserve naming through ABC using 'dress' command 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 15:05:07 +00:00
Clifford Wolf
643f858acf Bugfix in opt_expr handling of a<0 and a>=0 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:29:21 +01:00
whitequark
a9baee4b24 rename: add -src, for inferring names from source locations. 2018-12-05 20:35:13 +00:00
whitequark
d1f2cb01dc lut2mux: handle 1-bit INIT constant in $lut cells. 
This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
 2018-12-05 19:27:48 +00:00
whitequark
88217d0157 opt_lut: simplify type conversion. NFC. 2018-12-05 19:12:02 +00:00
Clifford Wolf
2d98db73e3 Rename opt_lut.cpp to opt_lut.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-05 18:03:58 +01:00
whitequark
45cb6200af opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. 2018-12-05 16:30:37 +00:00
whitequark
e603484070 opt_lut: always prefer to eliminate 1-LUTs. 
These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
 2018-12-05 16:30:37 +00:00
whitequark
59eea0183f opt_lut: collect and display statistics. 2018-12-05 16:30:37 +00:00
whitequark
e54c7e951c opt_lut: refactor to use a worker. NFC. 2018-12-05 16:30:37 +00:00
whitequark
9e072ec21f opt_lut: new pass, to combine LUTs for tighter packing. 2018-12-05 16:30:37 +00:00
Clifford Wolf
c800e3bb16 Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-04 23:30:23 +01:00
Clifford Wolf
70c417174d
Merge pull request from smunaut/min_ce_use 
Add option to only use DFFE is the resulting E signal would be use > N times
 2018-12-04 14:29:21 -08:00
Clifford Wolf
47c89d600c
Merge pull request from rafaeltp/master 
Splits SigSpec into bits before calling check_signal_in_fanout (solves )
 2018-12-01 04:11:19 +01:00
Sylvain Munaut
8d3ab626ea dff2dffe: Add option for unmap to only remove DFFE with low CE signal use 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-27 21:50:42 +01:00
Clifford Wolf
ab97eddee9 Add iteration limit to "opt_muxtree" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-20 17:56:47 +01:00
Niels Moseley
cfc9b9147c DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info. 2018-11-06 12:11:52 +01:00
Clifford Wolf
719e29404a Allow square brackets in liberty identifiers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-05 12:33:33 +01:00
Niels Moseley
04cd179696 Liberty file newline handling is more relaxed. More descriptive error message 2018-11-03 18:38:49 +01:00
Niels Moseley
d1e8249f9a Report an error when a liberty file contains pin references that reference non-existing pins 2018-11-03 18:07:51 +01:00
rafaeltp
f8b97e21f3 using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal 2018-10-21 11:32:44 -07:00
rafaeltp
7b964bfb83 cleaning up for PR 2018-10-20 18:02:59 -07:00
rafaeltp
ce069830c5 fixing code style 2018-10-20 17:57:26 -07:00