3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-08 10:25:19 +00:00
yosys/passes
Clifford Wolf a2154c1be0
Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata
memory_bram: Fix initdata bit order after shuffling
2018-12-16 15:53:44 +01:00
..
cmds rename: add -src, for inferring names from source locations. 2018-12-05 20:35:13 +00:00
equiv using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal 2018-10-21 11:32:44 -07:00
fsm Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
hierarchy Refactor code to avoid code duplication + added comments 2018-10-20 16:06:48 +02:00
memory memory_bram: Fix initdata bit order after shuffling 2018-12-11 21:02:49 +00:00
opt Merge pull request #720 from whitequark/master 2018-12-16 15:27:23 +01:00
proc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
sat Fixed minor typo in "sim" help message 2018-09-12 18:34:27 -04:00
techmap Merge pull request #714 from daveshah1/abc_preserve_naming 2018-12-16 15:41:30 +01:00
tests Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00