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yosys/passes
2018-12-05 16:30:37 +00:00
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cmds Merge pull request #625 from aman-goel/master 2018-09-14 12:36:13 +02:00
equiv using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal 2018-10-21 11:32:44 -07:00
fsm
hierarchy Refactor code to avoid code duplication + added comments 2018-10-20 16:06:48 +02:00
memory memory_bram: Reset make_outreg when growing read ports 2018-10-19 14:46:31 +01:00
opt opt_lut: new pass, to combine LUTs for tighter packing. 2018-12-05 16:30:37 +00:00
proc
sat
techmap Fix typo 2018-12-04 23:30:23 +01:00
tests