Martin Povišer
b6a9d78507
ql_dsp: Add -nocascade
2025-03-11 17:02:36 +01:00
Martin Povišer
4f2a06f55a
quicklogic: Complete DSPv2 flow
2025-03-11 16:37:43 +01:00
Martin Povišer
0d484818a7
ql_dsp_io_regs: Add DSPv2 support, adjust sim model
...
Add support for cell type dispatching of the new DSP block; adjust the
definition of MULT and MULTACC variants to support those instances
starting a cascading chain.
2025-03-11 16:35:38 +01:00
Martin Povišer
0180e8f30f
ql_dsp: Fix parameter widths, forbid self-cascading
2025-03-11 16:29:01 +01:00
Martin Povišer
26dc68086f
ql_dsp: Relax packing condition
2025-03-11 16:28:09 +01:00
Martin Povišer
7f833f4c37
ql_dsp: Add help
2025-03-11 16:26:54 +01:00
Martin Povišer
b230c00551
ql_dsp: Fix precondition for cascading
2025-03-11 10:35:31 +01:00
Martin Povišer
f157a868a3
ql_dsp: Add outer loop
2025-03-11 10:35:31 +01:00
Martin Povišer
fde681623c
ql_dsp: Improve cascading detection
2025-03-11 10:35:31 +01:00
Martin Povišer
0615209562
ql_dsp_macc: Support v2 DSP
2025-03-11 10:35:31 +01:00
Martin Povišer
947ca842f9
ql_dsp: Add promotion on cascading
2025-03-11 10:35:31 +01:00
Martin Povišer
c439f8c770
quicklogic: Fix cascading
2025-03-11 10:35:31 +01:00
Martin Povišer
6a3d1cc976
ql_dsp_macc: Avoid ID() macro for common IDs
2025-03-11 10:35:31 +01:00
Martin Povišer
0b8243b742
quicklogic: Revert changes to converge development
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
4cbc92f50f
quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
fb3ad314ba
quicklogic: ql_dsp_io_regs debug print
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
15b3ed4747
quicklogic: ql_dsp_macc set fractured mode
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
fcdd013c57
quicklogic: allow fractured mode on canonical dspv1 modules
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
62885f1de3
quicklogic: ql_dsp_simd remove unused MODE_BITS packing
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
f55da95ec8
quicklogic: update dspv2_sim.v to v1.1 Feb21
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
9b52ba8738
quicklogic: ql_dsp_simd add dspv2 support, fix dspv1
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
ed239b69fd
ql_dsp_macc: whitespace. NFC
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
651d5728d0
ql_dsp_macc: dspv2
2025-03-11 10:35:30 +01:00
Emil J. Tywoniak
47b270a03e
synth_quicklogic: enable dspv2 tests, fix -dspv2
2025-03-11 10:35:30 +01:00
Emil J. Tywoniak
c451d8ebb9
synth_quicklogic: add -dspv2 to opt into v2 DSP blocks
2025-03-11 10:35:30 +01:00
Martin Povišer
e1074e0e4e
qlf_k6n10f: Fix DSPV2 models
2025-03-11 10:35:01 +01:00
Martin Povišer
531374bec1
qlf_k6n10f: New ql_dsp pass, move to DSPV2
2025-03-11 10:35:01 +01:00
Martin Povišer
9f7cdd4bd4
Merge pull request #4262 from RoaLogic/master
...
MAX10 updates
2025-03-07 19:59:55 +01:00
N. Engelhardt
268a034b21
Merge pull request #4866 from YosysHQ/ql_ioff
...
add IOFF inference for qlf_k6n10f
2025-03-03 14:12:09 +00:00
N. Engelhardt
303a386ecc
create duplicate IOFFs if multiple output ports are connected to the same register
2025-01-31 11:28:57 +01:00
Krystine Sherwin
0ec5f1b756
pmgen: Move passes out of pmgen folder
...
- Techlib pmgens are now in relevant techlibs/*.
- `peepopt` pmgens are now in passes/opt.
- `test_pmgen` is still in passes/pmgen.
- Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location,
as well as the `#include`s.
- Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the
top level Makefile.
- Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file
name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir
$@))`.
2025-01-31 15:18:28 +13:00
N. Engelhardt
25b400982b
detect aliased I/O ports
2025-01-28 17:37:23 +01:00
N. Engelhardt
9da4fe747e
fix bus ioff inference
2025-01-28 11:23:36 +01:00
N. Engelhardt
1cf8e7c7db
add ioff inference for qlf_k6n10f
2025-01-24 21:17:15 +01:00
Emil J. Tywoniak
a58481e9b7
mark all hash_into methods nodiscard
2025-01-14 12:39:15 +01:00
Emil J
9f7040b3d1
Merge pull request #4683 from keszybz/use-SOURCE_DATE_EPOCH
...
Respect $SOURCE_DATE_EPOCH in generate_bram_types_sim.py
2025-01-10 23:43:26 +01:00
Emil J. Tywoniak
b9b9515bb0
hashlib: hash_eat -> hash_into
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
4e29ec1854
hashlib: acc -> eat
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
d071489ab1
hashlib: redo interface for flexibility
2024-12-18 14:49:25 +01:00
Miodrag Milanović
f4ddbc3994
Merge pull request #4771 from pepijndevos/famxtra
...
gowin: split cells_xtra by family
2024-12-08 19:46:36 +01:00
KrystalDelusion
c96d02b204
Merge pull request #4784 from YosysHQ/krys/reduce_warnings
...
Reduce number of warnings
2024-12-05 09:16:06 +13:00
Emil J
61a6567b9f
Merge pull request #4789 from YosysHQ/emil/sklansky-adder
...
Add a Sklansky option for `$lcu` mapping
2024-12-03 11:33:13 +01:00
Emil J. Tywoniak
fe64a714a9
techmap: add a Sklansky option for $lcu mapping
2024-12-02 11:34:58 +01:00
Emil J. Tywoniak
ebd7f2b366
techlibs: add _TECHMAP_DO_ to Han-Carlson adder
2024-12-02 09:54:24 +01:00
Krystine Sherwin
1de5d98ae2
Reduce comparisons of size_t and int
...
`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
2024-11-29 12:53:29 +13:00
Emil J. Tywoniak
4bf3677640
techmap: set Han-Carlson adder priority consistent with Kogge-Stone
2024-11-28 23:54:00 +01:00
Emil J. Tywoniak
6c78bd3637
techmap: add a Han-Carlson option for $lcu mapping
2024-11-28 15:33:21 +01:00
Pepijn de Vos
be836f4af3
gowin: split cells_xtra by family
2024-11-26 15:42:22 +01:00
Emil J
88abc4c20f
Merge pull request #4755 from pepijndevos/cells_xtra
...
Gowin: add GW2A and GW5A cells
2024-11-20 13:32:30 +01:00
Pepijn de Vos
b8329df1d0
add GW2A and GW5A cells
2024-11-17 20:25:11 +01:00
