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19183 commits

Author SHA1 Message Date
Akash Levy
3783a820ee Merge remote-tracking branch 'upstream' into merge3 2026-06-25 04:51:46 -07:00
Akash Levy
34e2e7ea2f
Merge pull request #192 from Silimate/large_mem_fix
Large mem fix with long long
2026-06-25 02:01:00 -07:00
Akash Levy
ff0014b925 Merge branch 'main' into large_mem_fix 2026-06-25 01:03:28 -07:00
Akash Levy
3876f53c73
Merge pull request #193 from Silimate/opt_compact_prefix_fix3
opt_compact_prefix fix 3
2026-06-25 00:49:38 -07:00
Akash Levy
2acff6a62c tests: fix sv_implicit_ports for port-resize log severity change
"Reduce port resize to warning" changed the resize message from
log_warning() to log(), which -q suppresses. Run the resize case without
-q and drop the stale "Warning: " prefix so the message is observed.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-24 23:52:31 -07:00
Akash Levy
139caf991c opt_compact_prefix: scope per-sweep clean to module, warn on non-convergence
Address review feedback on the fixpoint loop:
- Scope the per-sweep cleanup to the module under rewrite via
  Pass::call_on_module(..., "clean -purge") instead of running clean over
  the whole design selection. This avoids O(N^2) work across modules and
  keeps untouched modules' dangling cells until their own sweep, matching
  the original single-call behavior.
- Emit a log_warning if a module fails to reach a fixpoint within
  max_sweeps, so silent truncation of compaction is visible.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-24 23:52:30 -07:00
Akash Levy
2f8c9327b3 Verific: guard large-mem RAM width/word-count against int overflow
Address review feedback on the large-memory fix:
- comment explaining the 64-bit promotion and the remaining int limits
- log_error if the per-word width or word count would overflow RTLIL's
  int memory->width / memory->size fields, instead of silently truncating

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-24 23:33:55 -07:00
Akash Levy
da947b72d8 opt_compact_prefix fix 3 2026-06-24 22:40:21 -07:00
Akash Levy
9bfe32bffc Reduce port resize to warning 2026-06-24 17:21:38 -07:00
Akash Levy
2c790e52cd Large mem fix with long long 2026-06-24 17:21:10 -07:00
Miodrag Milanović
23aadd92ab
Merge pull request #5985 from YosysHQ/logid_left
Remove leftover use of log_id
2026-06-24 07:15:32 +00:00
Miodrag Milanovic
fd3ec58055 Remove leftover use of log_id 2026-06-24 08:04:48 +02:00
Akash Levy
d0879b7657 Bump abc to yosys-experimental head (8017a034)
Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-23 16:06:30 -07:00
KrystalDelusion
a07c484ce1
Merge pull request #5981 from YosysHQ/krys/equiv_opt_unknown
equiv_opt: Add ignore-unknown-cells
2026-06-23 19:58:30 +00:00
Miodrag Milanović
30d0b39a15
Merge pull request #5982 from YosysHQ/cleanup
File cleanup
2026-06-23 14:07:10 +00:00
Miodrag Milanovic
43d8a84bdc Add pre-commit config file 2026-06-23 07:30:54 +02:00
Miodrag Milanovic
55034dbe91 Remaining fix 2026-06-23 07:26:12 +02:00
Miodrag Milanovic
a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Miodrag Milanovic
3ac58b3ac1 Fixed line endings 2026-06-23 07:17:22 +02:00
Miodrag Milanovic
1f0ac8fffc Remove utf-8 marker 2026-06-23 07:14:20 +02:00
Miodrag Milanovic
f362e1db0e Remove executable flag from .v files 2026-06-23 07:12:43 +02:00
Akash Levy
e430753499
Merge pull request #191 from Silimate/fix_release
ci: fix silimate release
2026-06-22 19:42:44 -07:00
Mohamed Gaber
e804c1e3c2 ci: fix silimate release
- add option to test release flow without pushing to main
- add cmake to musllinux
- upgrade manylinux to rh-devtoolset-11
- add llvm to macos
- made CMake no longer error on unused parameters because we have some functions that are different from upstream but we'd like to keep the same signature
2026-06-23 05:14:22 +03:00
Akash Levy
bc56d9b3c0
Merge pull request #186 from Silimate/update_from_upstream
chore: merge upstream
2026-06-22 16:30:28 -07:00
KrystalDelusion
fe8f29b5f8
Merge pull request #5975 from dobios/patch-1
[docs] nit: least/most significant bits referred to using LSB/MSB instead of LSb/MSb
2026-06-22 23:21:34 +00:00
KrystalDelusion
e20a9168fb
Merge pull request #5971 from YosysHQ/krys/upto_indexing
write_verilog: Fix upto indexing for single bit
2026-06-22 23:04:16 +00:00
Krystine Sherwin
de6aa77dc8
equiv_opt: Add ignore-unknown-cells 2026-06-23 10:54:00 +12:00
Miodrag Milanović
0bd04dbae3
Merge pull request #5980 from YosysHQ/synth_intel
synth_intel: fix broken dsp mapping
2026-06-22 16:46:02 +00:00
Miodrag Milanovic
09eef69e31 synth_intel: fix broken dsp mapping 2026-06-22 17:51:26 +02:00
Mohamed Gaber
a8142b882f CMake: integrate backward-cpp 2026-06-22 18:24:29 +03:00
Miodrag Milanović
6edbcecc52
Merge pull request #5972 from YosysHQ/ci_mingw64
Add mingw64 build to CI
2026-06-22 14:54:56 +00:00
Miodrag Milanović
9139c94c8c
Merge pull request #5977 from YosysHQ/bitwuzla
smtbmc: support latest bitwuzla
2026-06-22 14:23:35 +00:00
Miodrag Milanovic
ed654de3d9 Add mingw64 build to CI 2026-06-22 16:22:13 +02:00
nella
57ec784983
Merge pull request #5953 from YosysHQ/nella/muxcover-enhancements
Add muxcover x peepopt regression test (#964).
2026-06-22 10:13:43 +00:00
nella
8f5d2d5894 Use -assert-none. 2026-06-22 11:12:00 +02:00
nella
3d0c868af0
Merge pull request #5952 from YosysHQ/nella/vector-index
Optimize upto vector indexing (Fix #892).
2026-06-22 09:05:26 +00:00
nella
6ffc938a75
Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup
Add warnings and errors to `sim -r` with VCD code path
2026-06-22 09:02:32 +00:00
Miodrag Milanović
f699624abf
Merge pull request #5978 from YosysHQ/remove_def
Remove define since snprintf is supported in MSVC now
2026-06-22 08:49:26 +00:00
Miodrag Milanovic
94e43f7675 Remove define since snprintf is supported in MSVC now 2026-06-22 09:50:39 +02:00
Miodrag Milanovic
ebcbc06951 smtbmc: support latest bitwuzla 2026-06-22 08:40:16 +02:00
Mohamed Gaber
0e7671c1b3 Merge remote-tracking branch 'origin/main' into update_from_upstream 2026-06-21 15:07:32 +03:00
Mohamed Gaber
2383dbda21 CMake: rework Silimate Verific file to work with Linux linker 2026-06-21 15:02:54 +03:00
Akash Levy
635c40ff46
Merge pull request #190 from Silimate/opt_first_fit_alloc
opt_first_fit_alloc
2026-06-21 02:06:12 -07:00
Akash Levy
8cdbd62394 opt_first_fit_alloc: address Greptile review
- pack_lanes: assert elem_w < 32 and pack the full element width instead
  of silently dropping bits >= 31.
- Remove the dead `cell` struct member and its unused assignment in run()
  (every emit helper shadows it with its own local `cell`).
- Decorrelate the pseudo-random bc bits from en (independent mix) so they
  no longer share an LFSR bit (e.g. en[7]/bc[0] for n=8).
- Add purpose comments to fingerprint_dsel and lane_of_bit.

Declined the std::stoi/std::stoll arg-parsing suggestion: it matches the
established convention in sibling passes (opt_argmax, opt_priority_onehot).

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-21 01:21:06 -07:00
Akash Levy
dc995eba98 opt_first_fit_alloc 2026-06-21 00:56:39 -07:00
Amelia Dobis
41566a6b70
more typo found 2026-06-19 17:47:39 -04:00
Amelia Dobis
54d43d85e3
[docs] nit: usign the right acronym to refer to the right thing
Tiny nit, but the description of `RTLIL::Wire` was using MSB and LSB to refer to the least and most significant *bits* of a wire and not Bytes, which should be referred to using LSb and MSb instead
2026-06-19 17:30:28 -04:00
Krystine Sherwin
b77bb851ed
tests: Add mixed_upto write_verilog test 2026-06-19 11:20:01 +12:00
Krystine Sherwin
338d4adef2
write_verilog: Fix upto indexing for single bit 2026-06-19 10:18:27 +12:00