Mohamed Gaber
0e7671c1b3
Merge remote-tracking branch 'origin/main' into update_from_upstream
2026-06-21 15:07:32 +03:00
Akash Levy
dc995eba98
opt_first_fit_alloc
2026-06-21 00:56:39 -07:00
Mohamed Gaber
e58125b605
Merge remote-tracking branch 'upstream/main' into silimate
2026-06-09 16:22:51 +03:00
Akash Levy
0c3446e8af
Fixups for Greptile
2026-06-01 19:03:52 -07:00
Akash Levy
9cc69a3c49
Improvement to opt_balance_tree
2026-06-01 17:56:44 -07:00
Akash Levy
6a8d800e63
Fixes for filtering small cases and catching more larger ones with trickier signatures
2026-05-27 03:40:44 -07:00
Akash Levy
89717069fe
Fixup
2026-05-27 01:51:54 -07:00
Akash Levy
e39395132d
opt_addcin pass
2026-05-27 00:39:25 -07:00
Akash Levy
2ba8a5cac6
opt parallel prefix and priority encoders
2026-05-20 12:14:50 -07:00
Akash Levy
8485d57841
opt_expr for constant comparisons
2026-04-20 02:03:35 -07:00
Miodrag Milanovic
ced2521b03
Convert gen-tests shell script to python
2026-04-16 11:00:44 +02:00
Robert O'Callahan
7f3b11e56b
Add test that connects a wire with init to a constant
2026-03-06 02:20:08 +00:00
Emil J
5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors
...
equiv_induct: error on missing model
2026-02-25 15:39:31 +01:00
Akash Levy
5f7658ca7c
Merge branch 'YosysHQ:main' into main
2026-02-05 13:10:34 -08:00
Emil J. Tywoniak
2efd0247a1
opt_hier: fix test
2026-02-03 18:10:29 +01:00
Emil J. Tywoniak
3bfeaee8ca
opt_expr: fix const lhs of $pow to $shl
2026-02-03 11:59:00 +01:00
Akash Levy
26f5ff3d74
Merge from upstream
2026-01-26 22:16:11 -08:00
Robert O'Callahan
32e96605d4
Don't update used_signals for retained wires in rmunused_module_signals.
...
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.
These updates will also make it difficult to process these wires in parallel.
2026-01-24 03:41:18 +00:00
Akash Levy
b11037e6c6
Merge remote-tracking branch 'upstream/main'
2026-01-21 15:13:57 -08:00
Natalia
d5e1647d11
fix tests with truncation issues
2026-01-14 18:03:30 -08:00
Natalia Kokoromyti
8b6925c5b0
Add opt_balance_tree pass for timing optimization
...
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.
The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.
Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases
Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
2026-01-13 14:20:11 -08:00
Akash Levy
e332ba807d
Merge branch 'YosysHQ:main' into main
2026-01-07 12:40:39 -08:00
Emil J
2e1a2cfacb
Merge pull request #5561 from YosysHQ/emil/opt_expr-test-avoid-multiple-drivers
...
opt_expr: avoid multiple drivers in test
2026-01-06 14:54:55 +01:00
Akash Levy
1941e8f042
Bump yosys and abc to latest
2025-12-25 03:46:16 -05:00
Emil J. Tywoniak
856d455065
opt_expr: avoid multiple drivers issue #4792 in combined assign tests
2025-12-19 18:32:56 +01:00
Emil J. Tywoniak
772d821fb0
opt_expr: reindent test
2025-12-19 18:32:56 +01:00
N. Engelhardt
45d654e2d7
avoid merging formal properties
2025-12-17 20:25:24 +01:00
Mohamed Gaber
dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11
2025-10-26 02:39:43 +03:00
Miodrag Milanović
4cdaac003f
Merge pull request #3991 from adrianparvino/alumacc-sign
...
alumacc: merge independent of sign
2025-10-08 13:02:10 +02:00
Akash Levy
16215b8786
Merge upstream
2025-09-29 20:58:56 -07:00
Martin Povišer
ffe2f7a16d
opt_hier: Fix two optimizations conflicting
...
Fix a conflict between the following two:
* propagation of tied-together inputs in
* propagation of unused inputs out
2025-09-29 12:27:27 +02:00
Akash Levy
652a9a63b2
Update to latest and fix all disabled tests
2025-09-28 01:33:08 -07:00
Akash Levy
8204fd1d0b
Update Yosys to latest
2025-09-06 16:49:39 -07:00
Emil J. Tywoniak
8333a83cef
opt_dff: more explicit testing, typo
2025-08-27 11:29:57 +02:00
Anhijkt
e1276560cd
opt_dff: add another test
2025-08-19 23:48:45 +03:00
Anhijkt
e486994f60
opt_dff: add test
2025-08-14 00:13:23 +03:00
Akash Levy
cc733fd11b
Merge from upstream
2025-07-30 22:50:14 -07:00
Robert O'Callahan
8b75c06141
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
Akash Levy
3cfbc0d7af
Merge branch 'YosysHQ:main' into main
2025-07-18 09:38:39 -07:00
Martin Povišer
22a44e4333
Start opt_hier
2025-07-05 16:45:52 +02:00
Akash Levy
7e9e4c7afe
Merge branch 'YosysHQ:main' into main
2025-06-23 02:30:24 -07:00
George Rennie
7160c91800
tests: add test for #5164 opt_dff -sat UAF
2025-06-06 23:46:23 +01:00
Akash Levy
c172eea61f
Merge branch 'YosysHQ:main' into main
2025-05-30 05:00:06 +02:00
George Rennie
353fd0f7f4
tests: test opt_expr for 32 bit unsigned shifts
2025-05-26 15:28:44 +01:00
Akash Levy
d520cb42cc
Merge branch 'YosysHQ:main' into main
2025-05-22 10:30:58 -07:00
George Rennie
d59380b3a0
tests: more complete testing of shift edgecases
2025-05-08 11:09:01 +02:00
George Rennie
af933b4f38
tests: check shifts by amounts that overflow int
2025-05-07 15:12:33 +02:00
Akash Levy
5e0d59ca90
Merge branch 'YosysHQ:main' into main
2025-04-28 18:12:42 -07:00
George Rennie
70a44f035c
tests: test opt_expr constant shift edge cases
2025-04-26 12:40:04 +02:00
Akash Levy
c0a6985adb
Merge branch 'YosysHQ:main' into main
2025-04-07 14:48:16 -07:00
