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Code Activity
2270 commits 124 branches 59 tags 44 MiB
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192 commits

Author SHA1 Message Date
luke whittlesey
2f90499e3d $mem cell in verilog backend : grouped writes by clock 2015-06-08 17:35:40 -04:00
luke whittlesey
a8fe040906 Bug fix in $mem verilog backend + changed tests/bram flow of make test. 2015-06-04 16:12:40 -04:00
Clifford Wolf
6061b7bd58 bugfix in blif front-end 2015-05-18 11:15:49 +02:00
Clifford Wolf
83499dc1ba added vloghtb test_febe.sh 2015-05-17 19:54:00 +02:00
Clifford Wolf
dae00e1d83 changed file() to open() in python scripts 2015-05-11 21:58:21 +02:00
Clifford Wolf
724cead61d Added "pmuxtree" command 2015-04-07 20:27:10 +02:00
Clifford Wolf
604c097f98 fix for python 2.6.6 2015-03-20 09:10:02 +01:00
Clifford Wolf
e9368a1d7e Various fixes for memories with offsets 2015-02-14 14:21:15 +01:00
Clifford Wolf
dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Clifford Wolf
913c304fe6 Added $meminit test case 2015-02-14 11:26:20 +01:00
Clifford Wolf
d58c3eca3a Some test related fixes 
(incl. removal of three bad test cases)
 2015-02-12 17:45:44 +01:00
Clifford Wolf
e666611534 Bugfix in resource sharing test 2015-01-27 19:30:06 +01:00
Clifford Wolf
8d295730e5 Refactoring of memory_bram and xilinx brams 2015-01-18 19:05:29 +01:00
Clifford Wolf
694cc01f1d improvements in muxtree/select_leaves test 2015-01-18 13:24:01 +01:00
Clifford Wolf
f630868bc9 Improvements in opt_muxtree 2015-01-18 12:57:36 +01:00
Clifford Wolf
dfa42e272c Tiny fix in vcdcd.pl 2015-01-13 12:59:29 +01:00
Clifford Wolf
daae35319b Added memory_bram "shuffle_enable" feature 2015-01-04 13:14:30 +01:00
Clifford Wolf
45918b8315 Added "memory -bram" 2015-01-03 17:40:20 +01:00
Clifford Wolf
a7fe87f888 Added memory_bram 'or_next_if_better' feature 2015-01-03 17:34:05 +01:00
Clifford Wolf
fd2c224c04 memory_bram transp support 2015-01-03 12:41:46 +01:00
Clifford Wolf
a7e43ae3d9 Progress in memory_bram 2015-01-03 10:57:01 +01:00
Clifford Wolf
90f4017703 Added proper clkpol support to memory_bram 2015-01-02 22:57:08 +01:00
Clifford Wolf
1dca7ae486 Fixes and improvements in bram test 2015-01-02 18:54:22 +01:00
Clifford Wolf
03b3c02540 Progress in bram testbench 2015-01-02 17:50:15 +01:00
Clifford Wolf
bbf89c4dc6 Progress in memory_bram 2015-01-02 13:59:47 +01:00
Clifford Wolf
36c20f2ede Progress in memory_bram 2015-01-02 00:07:44 +01:00
Clifford Wolf
24ae156a74 Progress in bram testbench 2015-01-01 20:58:33 +01:00
Clifford Wolf
340e769667 Bram testbench (incomplete) 2015-01-01 17:01:17 +01:00
Clifford Wolf
1e0f6b5ddb Added "yosys -qq" to also quiet warning messages 2014-11-09 11:02:20 +01:00
Clifford Wolf
f9c096eeda Added support for task and function args in parentheses 2014-10-27 13:21:57 +01:00
Clifford Wolf
7815f81c32 Added "synth" command 2014-09-14 16:09:06 +02:00
Clifford Wolf
76f8128123 Fixed autotest for non-basename arguments 2014-09-06 12:10:57 +02:00
Clifford Wolf
01ef34c147 Added tests/various/constmsk_test.ys 2014-09-04 15:07:30 +02:00
Clifford Wolf
88db09255b Added autotest -e (do not use -noexpr on write_verilog) 2014-08-30 18:34:07 +02:00
Clifford Wolf
c2df5b9175 Cosmetic changes to FSM tests 2014-08-21 17:40:49 +02:00
Clifford Wolf
28cf48e31f Some improvements in FSM mapping and recoding 2014-08-14 11:22:45 +02:00
Clifford Wolf
1dd8252169 Added test_verific mode to tests/fsm/generate.py 2014-08-12 15:43:30 +02:00
Clifford Wolf
cad98bcd89 Added multi-dim memory test (requires iverilog git head) 2014-08-12 10:37:47 +02:00
Clifford Wolf
788bd02f97 Fixed FSM mapping for multiple reset-like signals 2014-08-10 12:04:02 +02:00
Clifford Wolf
2faef89738 Some improvements in fsm_opt and fsm_map for FSM with unreachable states 2014-08-09 14:49:51 +02:00
Clifford Wolf
51aa5544fb Improved FSM tests 2014-08-08 15:08:11 +02:00
Clifford Wolf
c07774b0b6 Added FSM test bench 2014-08-08 13:12:18 +02:00
Clifford Wolf
91dd87e60b Improved scope resolution of local regs in Verilog+AST frontend 2014-08-05 12:15:53 +02:00
Clifford Wolf
0129d41efa Fixed AST handling of variables declared inside a functions main block 2014-08-05 08:35:51 +02:00
Clifford Wolf
358bf70a21 Added "wreduce" to some of the standard test benches 2014-08-03 20:22:33 +02:00
Clifford Wolf
5e641acc90 Consolidated hana test benches into fewer files 
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
    ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;

..etc..
 2014-08-01 03:57:37 +02:00
Clifford Wolf
03ef9a75c6 Added "test_autotb -n <num_iter>" option 2014-08-01 03:55:51 +02:00
Clifford Wolf
7d98645fe8 Added "make -j{N}" support to "make test" 2014-07-30 19:23:26 +02:00
Clifford Wolf
e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ 2014-07-29 21:12:50 +02:00
Clifford Wolf
27a872d1e7 Added support for "upto" wires to Verilog front- and back-end 2014-07-28 14:25:03 +02:00