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Refactoring of memory_bram and xilinx brams

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This commit is contained in:
Clifford Wolf 2015-01-18 19:05:29 +01:00
parent 694cc01f1d
commit 8d295730e5
6 changed files with 496 additions and 704 deletions
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4
tests/bram/generate.py
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@ -69,9 +69,9 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next):
print("endbram", file=dsc_f)
print("match bram_%02d_%02d" % (k1, k2), file=dsc_f)
if random.randrange(2):
non_zero_enables = [i for i in enable if i]
non_zero_enables = [chr(ord('A') + i) for i in range(len(enable)) if enable[i]]
if len(non_zero_enables):
print(" shuffle_enable %d" % random.choice(non_zero_enables), file=dsc_f)
print(" shuffle_enable %c" % random.choice(non_zero_enables), file=dsc_f)
if or_next:
print(" or_next_if_better", file=dsc_f)
print("endmatch", file=dsc_f)

2
tests/tools/cmp_tbdata.c
View file

@ -53,6 +53,8 @@ int main(int argc, char **argv)
// here means we don't care about the result.
if (buffer1[i] == 'z' || buffer1[i] == 'x')
continue;
if (buffer1[i] == 'Z' || buffer1[i] == 'X')
continue;
check(buffer1[i] == buffer2[i]);
}