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	Added FSM test bench
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					 2 changed files with 113 additions and 0 deletions
				
			
		
							
								
								
									
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								tests/fsm/generate.py
									
										
									
									
									
										Normal file
									
								
							
							
						
						
									
										83
									
								
								tests/fsm/generate.py
									
										
									
									
									
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#!/usr/bin/python
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from __future__ import division
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from __future__ import print_function
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import sys
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import random
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from contextlib import contextmanager
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@contextmanager
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def redirect_stdout(new_target):
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    old_target, sys.stdout = sys.stdout, new_target
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    try:
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        yield new_target
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    finally:
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        sys.stdout = old_target
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def random_expr(variables):
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    c = random.choice(['bin', 'uni', 'var', 'const'])
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    if c == 'bin':
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        op = random.choice(['+', '-', '*', '<', '<=', '==', '!=', '>=', '>', '<<', '>>', '<<<', '>>>', '|', '&', '^', '~^', '||', '&&'])
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        return "(%s %s %s)" % (random_expr(variables), op, random_expr(variables))
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    if c == 'uni':
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        op = random.choice(['+', '-', '~', '|', '&', '^', '~^', '!', '$signed', '$unsigned'])
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        return "%s(%s)" % (op, random_expr(variables))
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    if c == 'var':
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        return random.choice(variables)
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    if c == 'const':
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        bits = random.randint(1, 32)
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        return "%d'd%s" % (bits, random.randint(0, 2**bits-1))
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    raise AssertionError
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for idx in range(100):
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    with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f):
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        print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx))
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        print('  input clk, rst;')
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        variables=['a', 'b', 'c', 'x', 'y', 'z']
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        print('  input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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        print('  input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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        print('  input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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        print('  output reg%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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        print('  output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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        print('  output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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        print('  reg [15:0] state;')
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        states=[]
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        for i in range(random.randint(2, 10)):
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            n = random.randint(0, 2**16-1)
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            if n not in states:
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                states.append(n)
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        print('  always @(posedge clk) begin')
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        print('    if (rst) begin')
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        print('      x <= %d;' % random.randint(0, 2**31-1))
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        print('      y <= %d;' % random.randint(0, 2**31-1))
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        print('      z <= %d;' % random.randint(0, 2**31-1))
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        print('      state <= %d;' % random.choice(states))
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        print('    end else begin')
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        print('      case (state)')
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        for state in states:
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            print('        %d: begin' % state)
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            for var in ('x', 'y', 'z'):
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                print('            %s <= %s;' % (var, random_expr(variables)))
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            next_states = states[:]
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            for i in range(random.randint(0, len(states))):
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                next_state = random.choice(next_states)
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                next_states.remove(next_state)
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                print('            if ((%s) %s (%s)) state <= %s;' % (random_expr(variables),
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                        random.choice(['<', '<=', '>=', '>']), random_expr(variables), next_state))
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            print('          end')
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        print('      endcase')
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        print('    end')
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        print('  end')
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        print('endmodule')
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    with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f):
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        print('read_verilog temp/uut_%05d.v' % idx)
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        print('proc;;')
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        print('copy uut_%05d gold' % idx)
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        print('rename uut_%05d gate' % idx)
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        print('cd gate')
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        print('opt; wreduce; share; opt; fsm;;')
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        print('cd ..')
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        print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
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        print('sat -verify -seq 5 -set-at 1 in_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter')
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										30
									
								
								tests/fsm/run-test.sh
									
										
									
									
									
										Executable file
									
								
							
							
						
						
									
										30
									
								
								tests/fsm/run-test.sh
									
										
									
									
									
										Executable file
									
								
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#!/bin/bash
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# run this test many times:
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# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
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set -e
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rm -rf temp
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mkdir -p temp
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echo "generating tests.."
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python generate.py
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{
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	all_targets="all_targets:"
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	echo "all: all_targets"
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	for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do
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		idx=$( printf "%05d" $i )
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		echo "temp/uut_${idx}.log: temp/uut_${idx}.ys temp/uut_${idx}.v"
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		echo "	@echo -n '[$i]'"
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		echo "	@../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys"
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		all_targets="$all_targets temp/uut_${idx}.log"
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	done
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	echo "$all_targets"
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} > temp/makefile
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echo "running tests.."
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${MAKE:-make} -f temp/makefile
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echo
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exit 0
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