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Bug fix in $mem verilog backend + changed tests/bram flow of make test.

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This commit is contained in:
luke whittlesey 2015-06-04 14:56:13 -04:00
parent 08f9b38a9c
commit a8fe040906
2 changed files with 20 additions and 16 deletions
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6
tests/bram/run-single.sh
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@ -1,7 +1,9 @@
#!/bin/bash
set -e
../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \
-l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v
../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full; write_verilog temp/synth_${1}_${2}_stage0.v" \
-l temp/synth_${1}_${2}_stage0.log temp/brams_${1}.v
../../yosys -qq -p "proc; opt; memory -nomap; opt -fast -full; write_verilog -nomem temp/synth_${1}_${2}.v" \
-l temp/synth_${1}_${2}.log temp/synth_${1}_${2}_stage0.v
iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1ns -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \
temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v
temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt