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Code Activity
7631 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
2cb2116b4c Use "abc9_period" attribute for delay target 2019-10-07 15:03:44 -07:00
Eddie Hung
90a954bb9c Get rid of latch_* in write_xaiger 2019-10-07 13:09:13 -07:00
Eddie Hung
bae3d8705d Update comments in abc9_map.v 2019-10-07 12:54:45 -07:00
Eddie Hung
1dc22607c3 Remove -D_ABC9 2019-10-07 12:21:52 -07:00
Eddie Hung
1504ca2cd9 Remove "write_xaiger -zinit" 2019-10-07 11:58:49 -07:00
Eddie Hung
e1554b56dd Add comment on default flop init 2019-10-07 11:56:17 -07:00
Eddie Hung
d9fba95177 Get rid of output_port lookup 2019-10-07 11:49:06 -07:00
Eddie Hung
3879ca1398 Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
Eddie Hung
3c6e5d82a6 Error if $currQ not found 2019-10-05 09:06:13 -07:00
Eddie Hung
a2ef93f03a abc -> abc9 2019-10-04 17:56:38 -07:00
Eddie Hung
f0cadb0de8 Fix from merge 2019-10-04 17:52:19 -07:00
Eddie Hung
bbc0e06af3 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-04 17:39:08 -07:00
Eddie Hung
0acc51c3d8 Add temporary abc9 -nomfs and use for synth_xilinx -abc9 2019-10-04 17:35:43 -07:00
Eddie Hung
d4212d128b Use read_args for read_verilog 2019-10-04 17:27:05 -07:00
Eddie Hung
9c23811839 Remove DSP48E1 from *_cells_xtra.v 2019-10-04 17:26:42 -07:00
Eddie Hung
7959e9d6b2 Fix merge issues 2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung
74ef8feeaf Fix xilinx_dsp for unsigned extensions 2019-10-04 16:46:15 -07:00
Eddie Hung
6bf7114bbd Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again 2019-10-04 16:45:36 -07:00
Eddie Hung
279fd22ddf Add Const::{begin,end,empty}() 2019-10-04 15:00:57 -07:00
Eddie Hung
aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung
9fef1df3c1 Panic over. Model was elsewhere. Re-arrange for consistency 2019-10-04 10:48:44 -07:00
Eddie Hung
4e11782cde Oops 2019-10-04 10:36:02 -07:00
Eddie Hung
c0f54d3fd5 Ohmilord this wasn't added all this time!?! 2019-10-04 10:34:16 -07:00
Eddie Hung
549d6ea467 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-03 10:55:23 -07:00
Eddie Hung
655f1b2ac5 English 2019-10-03 10:11:25 -07:00
Clifford Wolf
2ed2e9c3e8 Change smtbmc "Warmup failed" status to "PREUNSAT" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 14:59:07 +02:00
Clifford Wolf
17cb916cc8 Update ABC to git rev 623b5e8 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 14:05:21 +02:00
Clifford Wolf
be8efd7c7b Bump version 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 12:26:08 +02:00
Clifford Wolf
468b8a5178
Merge pull request #1419 from YosysHQ/eddie/lazy_derive 
module->derive() to be lazy and not touch ast if already derived
 2019-10-03 12:06:12 +02:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select 
Add -select option to aigmap
 2019-10-03 11:54:04 +02:00
Clifford Wolf
afdc990595
Merge pull request #1429 from YosysHQ/clifford/checkmapped 
Add "check -mapped"
 2019-10-03 11:50:53 +02:00
Clifford Wolf
3e27b2846b Add "check -allow-tbuf" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 11:49:56 +02:00
David Shah
e0a6742935
Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16 
ecp5: Add support for mapping 36-bit wide PDP BRAMs
 2019-10-03 09:53:45 +01:00
Eddie Hung
278533fe59
Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire 
RFC: techmap to recognise wires named "_TECHMAP_REPLACE_.<suffix>"
 2019-10-02 19:40:39 -07:00
Eddie Hung
62c66406ad log_dump() to support State enum 2019-10-02 17:49:07 -07:00
Eddie Hung
265a655ef9 Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf 2019-10-02 12:43:35 -07:00
Eddie Hung
a4f2f7d23c Extend test with renaming cells with prefix too 2019-10-02 12:43:18 -07:00
Clifford Wolf
6028f5df1a
Merge pull request #1428 from YosysHQ/clifford/fixbtor 
Fix btor back-end to use "state" instead of "input" for undef init bits
 2019-10-02 13:48:09 +02:00
Clifford Wolf
45e4c040d7 Add "check -mapped" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-02 13:35:03 +02:00
Clifford Wolf
a84a2d74c7 Fix btor back-end to use "state" instead of "input" for undef init bits 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-02 12:48:04 +02:00
Eddie Hung
5299884f04 More fixes 2019-10-01 13:41:08 -07:00
Eddie Hung
03ebe43e3e Escape Verilog identifiers for legality outside of Yosys 2019-10-01 13:05:56 -07:00
Miodrag Milanović
da347b9f7e
Merge pull request #1426 from YosysHQ/mmicko/fix_environ 
Define environ, fixes #1424
 2019-10-01 19:50:37 +02:00
Miodrag Milanovic
c026579c20 Define environ, fixes #1424 2019-10-01 18:45:07 +02:00
David Shah
b424d374db ecp5: Fix shuffle_enable port 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 14:14:46 +01:00
David Shah
7a1538cd36 ecp5: Add support for mapping 36-bit wide PDP BRAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 13:46:36 +01:00
Eddie Hung
369652d4b9 Add test 2019-09-30 17:20:39 -07:00
Eddie Hung
edc3780723 techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias 2019-09-30 17:20:12 -07:00
Eddie Hung
1b96d29174 No need to punch ports at all 2019-09-30 17:02:20 -07:00