1921 commits

Author	SHA1	Message	Date
Clifford Wolf	a381188b92	Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys	2017-10-03 18:23:45 +02:00
Udi Finkelstein	eb40278a16	Turned a few member functions into const, esp. dumpAst(), dumpVlog().	2017-09-30 07:37:38 +03:00
Udi Finkelstein	72a08eca3d	Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution ... (Oreilly 'Flex & Bison' page 189)	2017-09-30 06:39:07 +03:00
Clifford Wolf	dbfd8460a9	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
Udi Finkelstein	e951ac0dfb	$size() now works correctly for all cases! ... It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.	2017-09-26 20:34:24 +03:00
Udi Finkelstein	6ddc6a7af4	$size() seems to work now with or without the optional parameter. ... Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.	2017-09-26 19:18:25 +03:00
Udi Finkelstein	7e391ba904	enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog	2017-09-26 09:19:56 +03:00
Udi Finkelstein	2dea42e903	Added $bits() for memories as well.	2017-09-26 09:11:25 +03:00
Udi Finkelstein	17f8b41605	$size() now works with memories as well!	2017-09-26 08:36:45 +03:00
Udi Finkelstein	64eb8f29ad	Add $size() function. At the moment it works only on expressions, not on memories.	2017-09-26 06:25:42 +03:00
Clifford Wolf	30396270a2	Increase maximum LUT size in blifparse to 12 bits	2017-09-27 15:27:42 +02:00
Clifford Wolf	91d9c50bb3	Parse reals as string in JSON front-end	2017-09-26 14:37:03 +02:00
Clifford Wolf	2c04d883b1	Minor coding style fix	2017-09-26 13:50:14 +02:00
Clifford Wolf	cb1d439d10	Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master	2017-09-26 13:48:13 +02:00
Clifford Wolf	2cc09161ff	Fix ignoring of simulation timings so that invalid module parameters cause syntax errors	2017-09-26 01:52:59 +02:00
combinatorylogic	64ca0be971	Adding support for string macros and macros with arguments after include	2017-09-21 18:25:02 +01:00
Robert Ou	366ce87cff	json: Parse inout correctly rather than as an output	2017-08-14 12:09:03 -07:00
Clifford Wolf	15073790bf	Add merging of "past FFs" to verific importer	2017-07-29 00:10:38 +02:00
Clifford Wolf	d4b9602cbd	Add minimal support for PSL in VHDL via Verific	2017-07-28 17:39:49 +02:00
Clifford Wolf	5a828fff34	Improve Verific HDL language options	2017-07-28 15:32:54 +02:00
Clifford Wolf	acd6cfaf67	Fix handling of non-user-declared Verific netbus	2017-07-28 11:31:27 +02:00
Clifford Wolf	c1cfca8f54	Improve Verific SVA importer	2017-07-27 14:05:09 +02:00
Clifford Wolf	2336d5508b	Add log_warning_noprefix() API, Use for Verific warnings and errors	2017-07-27 12:17:04 +02:00
Clifford Wolf	d9641621d9	Add "verific -import -n" and "verific -import -nosva"	2017-07-27 11:54:45 +02:00
Clifford Wolf	90d8329f64	Improve Verific SVA import: negedge and $past	2017-07-27 11:40:07 +02:00
Clifford Wolf	147ff96ba3	Improve Verific SVA importer	2017-07-27 10:39:39 +02:00
Clifford Wolf	530040ba6f	Improve Verific bindings (mostly related to SVA)	2017-07-26 18:00:01 +02:00
Clifford Wolf	abd3b4e8e7	Improve "help verific" message	2017-07-25 15:13:22 +02:00
Clifford Wolf	6dbe1d4c92	Add "verific -extnets"	2017-07-25 14:53:11 +02:00
Clifford Wolf	c97c92e4ec	Improve "verific -all" handling	2017-07-25 13:33:25 +02:00
Clifford Wolf	41be530c4e	Add "verific -import -d <dump_file"	2017-07-24 13:57:16 +02:00
Clifford Wolf	92d3aad670	Add "verific -import -flatten" and "verific -import -v"	2017-07-24 11:29:06 +02:00
Clifford Wolf	5be535517c	Add "verific -import -k"	2017-07-22 16:16:44 +02:00
Clifford Wolf	2785aaffeb	Improve docs for verific bindings, add simply sby example	2017-07-22 11:58:51 +02:00
Clifford Wolf	36cf18ac4c	Fix "read_blif -wideports" handling of cells with wide ports	2017-07-21 16:21:12 +02:00
Clifford Wolf	26766da343	Add a paragraph about pre-defined macros to read_verilog help message	2017-07-21 14:34:53 +02:00
Clifford Wolf	9557fd2a36	Add attributes and parameter support to JSON front-end	2017-07-10 13:17:38 +02:00
Clifford Wolf	4b2d1fe688	Add JSON front-end	2017-07-08 16:40:40 +02:00
Clifford Wolf	28039c3063	Add Verific Release information to log	2017-07-04 20:01:30 +02:00
Clifford Wolf	8f8baccfde	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"	2017-06-07 12:30:24 +02:00
Clifford Wolf	129984e115	Fix handling of Verilog ~& and ~| operators	2017-06-01 12:43:21 +02:00
Clifford Wolf	e91548b33e	Add support for localparam in module header	2017-04-30 17:20:30 +02:00
Clifford Wolf	f0db8ffdbc	Add support for `resetall compiler directive	2017-04-26 16:09:41 +02:00
Clifford Wolf	088f9c9cab	Fix verilog pre-processor for multi-level relative includes	2017-03-14 17:30:20 +01:00
Clifford Wolf	5b3b5ffc8c	Allow $anyconst, etc. in non-formal SV mode	2017-03-01 10:47:05 +01:00
Clifford Wolf	5f1d0b1024	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00
Clifford Wolf	00dba4c197	Add support for SystemVerilog unique, unique0, and priority case	2017-02-23 16:33:19 +01:00
Clifford Wolf	1e927a51d5	Preserve string parameters	2017-02-23 15:39:13 +01:00
Clifford Wolf	34d4e72132	Added SystemVerilog support for ++ and --	2017-02-23 11:21:33 +01:00
Clifford Wolf	4fb8007171	Fix incorrect "incompatible re-declaration of wire" error in tasks/functions	2017-02-14 15:10:59 +01:00