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https://github.com/YosysHQ/yosys
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Add minimal support for PSL in VHDL via Verific
This commit is contained in:
Clifford Wolf
parent
4cf890dac1
commit
d4b9602cbd
1 changed files with 155 additions and 19 deletions
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@ -167,7 +167,7 @@ struct VerificImporter
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PRIM_NONCONS_REP, PRIM_GOTO_REP
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};
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for (int p : sva_prims)
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for (int p : psl_prims)
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verific_psl_prims.insert(p);
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}
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@ -1051,20 +1051,20 @@ struct VerificImporter
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if (!mode_gates) {
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if (import_netlist_instance_cells(inst, inst_name))
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continue;
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if (inst->IsOperator())
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if (inst->IsOperator() && !verific_sva_prims.count(inst->Type()) && !verific_psl_prims.count(inst->Type()))
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log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name());
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} else {
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if (import_netlist_instance_gates(inst, inst_name))
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continue;
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}
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if (inst->Type() == PRIM_SVA_ASSERT)
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if (inst->Type() == PRIM_SVA_ASSERT || inst->Type() == PRIM_PSL_ASSERT)
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sva_asserts.insert(inst);
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if (inst->Type() == PRIM_SVA_ASSUME)
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if (inst->Type() == PRIM_SVA_ASSUME || inst->Type() == PRIM_PSL_ASSUME)
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sva_assumes.insert(inst);
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if (inst->Type() == PRIM_SVA_COVER)
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if (inst->Type() == PRIM_SVA_COVER || inst->Type() == PRIM_PSL_COVER)
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sva_covers.insert(inst);
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if (inst->Type() == PRIM_SVA_PAST && !mode_nosva)
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@ -1084,6 +1084,32 @@ struct VerificImporter
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continue;
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}
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if (inst->Type() == OPER_PSLPREV && !mode_nosva)
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{
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Net *clock = inst->GetClock();
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if (!clock->IsConstant())
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{
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VerificClockEdge clock_edge(this, clock->Driver());
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SigSpec sig_d, sig_q;
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for (int i = 0; i < int(inst->InputSize()); i++) {
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sig_d.append(net_map_at(inst->GetInputBit(i)));
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sig_q.append(net_map_at(inst->GetOutputBit(i)));
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}
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if (verbose)
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log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clock_edge.posedge ? "pos" : "neg",
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log_signal(sig_d), log_signal(sig_q), log_signal(clock_edge.clock_sig));
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module->addDff(NEW_ID, clock_edge.clock_sig, sig_d, sig_q, clock_edge.posedge);
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if (!mode_keep)
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continue;
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}
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}
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if (!mode_keep && (verific_sva_prims.count(inst->Type()) || verific_psl_prims.count(inst->Type()))) {
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if (verbose)
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log(" skipping SVA/PSL cell in non k-mode\n");
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@ -1156,22 +1182,93 @@ struct VerificImporter
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}
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};
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Net *verific_follow_inv(Net *w)
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{
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if (w == nullptr || w->IsMultipleDriven())
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return nullptr;
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Instance *i = w->Driver();
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if (i == nullptr || i->Type() != PRIM_INV)
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return nullptr;
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return i->GetInput();
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}
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Net *verific_follow_pslprev(Net *w)
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{
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if (w == nullptr || w->IsMultipleDriven())
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return nullptr;
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Instance *i = w->Driver();
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if (i == nullptr || i->Type() != OPER_PSLPREV || i->InputSize() != 1)
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return nullptr;
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return i->GetInputBit(0);
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}
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Net *verific_follow_inv_pslprev(Net *w)
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{
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w = verific_follow_inv(w);
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return verific_follow_pslprev(w);
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}
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VerificClockEdge::VerificClockEdge(VerificImporter *importer, Instance *inst)
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{
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log_assert(importer != nullptr);
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log_assert(inst != nullptr);
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log_assert(inst->Type() == PRIM_SVA_POSEDGE);
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clock_net = inst->GetInput();
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posedge = true;
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// SVA posedge/negedge
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if (inst->Type() == PRIM_SVA_POSEDGE)
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{
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clock_net = inst->GetInput();
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posedge = true;
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Instance *driver = clock_net->Driver();
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if (!clock_net->IsMultipleDriven() && driver && driver->Type() == PRIM_INV) {
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clock_net = driver->GetInput();
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posedge = false;
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Instance *driver = clock_net->Driver();
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if (!clock_net->IsMultipleDriven() && driver && driver->Type() == PRIM_INV) {
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clock_net = driver->GetInput();
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posedge = false;
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}
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clock_sig = importer->net_map_at(clock_net);
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return;
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}
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clock_sig = importer->net_map_at(clock_net);
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// VHDL-flavored PSL clock
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if (inst->Type() == PRIM_AND)
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{
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Net *w1 = inst->GetInput1();
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Net *w2 = inst->GetInput2();
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clock_net = verific_follow_inv_pslprev(w1);
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if (clock_net == w2) {
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clock_sig = importer->net_map_at(clock_net);
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posedge = true;
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return;
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}
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clock_net = verific_follow_inv_pslprev(w2);
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if (clock_net == w1) {
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clock_sig = importer->net_map_at(clock_net);
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posedge = true;
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return;
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}
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clock_net = verific_follow_pslprev(w1);
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if (clock_net == verific_follow_inv(w2)) {
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clock_sig = importer->net_map_at(clock_net);
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posedge = false;
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return;
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}
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clock_net = verific_follow_pslprev(w2);
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if (clock_net == verific_follow_inv(w1)) {
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clock_sig = importer->net_map_at(clock_net);
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posedge = false;
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return;
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}
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log_abort();
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}
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}
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struct VerificSvaImporter
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@ -1254,11 +1351,15 @@ struct VerificSvaImporter
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{
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Instance *inst = net_to_ast_driver(n);
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// Regular expression
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if (inst == nullptr) {
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sequence_cond(seq, importer->net_map_at(n));
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return;
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}
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// SVA Primitives
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if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION)
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{
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parse_sequence(seq, inst->GetInput1());
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@ -1310,6 +1411,33 @@ struct VerificSvaImporter
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return;
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}
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// PSL Primitives
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if (inst->Type() == PRIM_ALWAYS)
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{
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parse_sequence(seq, inst->GetInput());
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return;
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}
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if (inst->Type() == PRIM_IMPL)
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{
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parse_sequence(seq, inst->GetInput1());
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seq.sig_en = module->And(NEW_ID, seq.sig_en, seq.sig_a);
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parse_sequence(seq, inst->GetInput2());
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return;
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}
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if (inst->Type() == PRIM_SUFFIX_IMPL)
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{
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parse_sequence(seq, inst->GetInput1());
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seq.sig_en = module->And(NEW_ID, seq.sig_en, seq.sig_a);
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sequence_ff(seq);
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parse_sequence(seq, inst->GetInput2());
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return;
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}
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// Handle unsupported primitives
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if (!importer->mode_keep)
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log_error("Unsupported Verific SVA primitive %s of type %s.\n", inst->Name(), inst->View()->Owner()->Name());
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log_warning("Unsupported Verific SVA primitive %s of type %s.\n", inst->Name(), inst->View()->Owner()->Name());
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@ -1323,20 +1451,24 @@ struct VerificSvaImporter
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// parse SVA property clock event
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Instance *at_node = get_ast_input(root);
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log_assert(at_node && at_node->Type() == PRIM_SVA_AT);
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log_assert(at_node && (at_node->Type() == PRIM_SVA_AT || at_node->Type() == PRIM_AT));
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VerificClockEdge clock_edge(importer, get_ast_input1(at_node));
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VerificClockEdge clock_edge(importer, at_node->Type() == PRIM_SVA_AT ? get_ast_input1(at_node) : at_node->GetInput2()->Driver());
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clock = clock_edge.clock_sig;
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clock_posedge = clock_edge.posedge;
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// parse disable_iff expression
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Net *sequence_net = at_node->GetInput2();
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Net *sequence_net = at_node->Type() == PRIM_SVA_AT ? at_node->GetInput2() : at_node->GetInput1();
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Instance *sequence_node = net_to_ast_driver(sequence_net);
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if (sequence_node && sequence_node->Type() == PRIM_SVA_DISABLE_IFF) {
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disable_iff = importer->net_map_at(sequence_node->GetInput1());
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sequence_net = sequence_node->GetInput2();
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} else
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if (sequence_node && sequence_node->Type() == PRIM_ABORT) {
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disable_iff = importer->net_map_at(sequence_node->GetInput2());
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sequence_net = sequence_node->GetInput1();
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}
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// parse SVA sequence into trigger signal
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@ -1503,18 +1635,22 @@ struct VerificPass : public Pass {
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log(" -extnets\n");
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log(" Resolve references to external nets by adding module ports as needed.\n");
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log("\n");
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log(" -nosva\n");
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log(" Ignore SVA properties, do not infer checker logic. (This also disables\n");
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log(" PSL properties in -vhdpsl mode.)\n");
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log("\n");
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log(" -v\n");
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log(" Verbose log messages.\n");
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log("\n");
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log("The following additional import options are useful for debugging the Verific\n");
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log("bindings (for Yosys and/or Verific developers):\n");
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log("\n");
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log(" -k\n");
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log(" Keep going after an unsupported verific primitive is found. The\n");
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log(" unsupported primitive is added as blockbox module to the design.\n");
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log(" This will also add all SVA related cells to the design parallel to\n");
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log(" the checker logic inferred by it.\n");
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log("\n");
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log(" -nosva\n");
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log(" Ignore SVA properties, do not infer checker logic.\n");
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log("\n");
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log(" -n\n");
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log(" Keep all Verific names on instances and nets. By default only\n");
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log(" user-declared names are preserved.\n");
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