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Improve Verific HDL language options
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acd6cfaf67
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@ -1473,12 +1473,12 @@ struct VerificPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv} <verilog-file>..\n");
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log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..\n");
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log("\n");
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log("Load the specified Verilog/SystemVerilog files into Verific.\n");
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log("\n");
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log("\n");
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log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdpsl} <vhdl-file>..\n");
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log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl|-vhdpsl} <vhdl-file>..\n");
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log("\n");
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log("Load the specified VHDL files into Verific.\n");
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log("\n");
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@ -1576,7 +1576,7 @@ struct VerificPass : public Pass {
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return;
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}
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if (GetSize(args) > argidx && args[argidx] == "-sv") {
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if (GetSize(args) > argidx && (args[argidx] == "-sv2012" || args[argidx] == "-sv")) {
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for (argidx++; argidx < GetSize(args); argidx++)
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if (!veri_file::Analyze(args[argidx].c_str(), veri_file::SYSTEM_VERILOG))
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log_cmd_error("Reading `%s' in SYSTEM_VERILOG mode failed.\n", args[argidx].c_str());
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@ -1607,7 +1607,7 @@ struct VerificPass : public Pass {
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return;
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}
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if (GetSize(args) > argidx && args[argidx] == "-vhdl2008") {
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if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) {
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vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
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for (argidx++; argidx < GetSize(args); argidx++)
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if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008))
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