Udi Finkelstein 72a08eca3d Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution ... (Oreilly 'Flex & Bison' page 189)		2017-09-30 06:39:07 +03:00
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ast	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
blif	Increase maximum LUT size in blifparse to 12 bits	2017-09-27 15:27:42 +02:00
ilang	Added avail params to ilang format, check module params in 'hierarchy -check'	2016-10-22 11:05:49 +02:00
json	Parse reals as string in JSON front-end	2017-09-26 14:37:03 +02:00
liberty	Added liberty parser support for types within cell decls	2016-09-23 13:53:23 +02:00
verific	Add merging of "past FFs" to verific importer	2017-07-29 00:10:38 +02:00
verilog	Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution	2017-09-30 06:39:07 +03:00
vhdl2verilog	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00