Robert O'Callahan
290fb0556d
Prevent race on num_active_worker_threads_.
...
The core issue here is that we need to ensure `num_active_worker_threads_`
is read before incrementing `done_workers`. See the comments
added in this PR to explain why, and why the resulting code is
race-free.
2026-03-24 22:20:18 +00:00
Miodrag Milanović
66306a8ca3
Merge pull request #5769 from Silimate/optimize_sim_pass
...
sim: early return from checkSignals in sim mode
2026-03-23 17:19:26 +00:00
Miodrag Milanović
cc915b4c76
Merge pull request #5717 from zaun/latch-support
...
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
2026-03-23 16:51:30 +00:00
Emil J
b44188110b
Merge pull request #5764 from YosysHQ/emil/constmap-error
...
constmap: error if no -cell set
2026-03-23 15:15:04 +00:00
Emil J
7b2ab9b245
Merge pull request #5763 from YosysHQ/emil/c-slow-init
...
genrtlil: fast memory initialization
2026-03-23 10:21:21 +00:00
tondapusili
69219e6be0
sim: early-return from checkSignals in sim mode
2026-03-20 12:32:49 -07:00
Miodrag Milanović
5fd39ff3e1
Merge pull request #5766 from YosysHQ/upgrade_ci
...
Upgrade CI actions
2026-03-19 18:06:50 +00:00
Emil J
dc77140275
Merge pull request #5731 from YosysHQ/nella/wall-clock
...
Implement wall clock time measurement
2026-03-19 16:21:26 +00:00
nella
ee0461eb00
Change time log format.
2026-03-19 14:38:22 +01:00
nella
d6ab610622
Implement wall clock time meas.
2026-03-19 14:38:22 +01:00
Miodrag Milanovic
2a8024ea4a
Upgrade CI actions
2026-03-19 12:22:57 +01:00
Lofty
f560cba952
Merge pull request #5757 from YosysHQ/lofty/abc9-refactor-3
...
abc9: remove -fast [sc-269]
2026-03-19 08:41:45 +00:00
Lofty
27210627e5
abc9: remove -fast
2026-03-19 07:30:23 +00:00
Lofty
8d1d5a25e5
Merge pull request #5760 from YosysHQ/lofty/abc-refactor-2
...
abc: remove -S [sc-269]
2026-03-19 07:26:54 +00:00
Lofty
05de1c4ae2
Merge pull request #5759 from YosysHQ/lofty/abc9-refactor-4
...
abc9: remove abc9.if.C [sc-269]
2026-03-19 07:26:37 +00:00
Emil J. Tywoniak
7aaa0621d3
constmap: error if no -cell set
2026-03-19 00:01:14 +01:00
Emil J
9746bd3897
Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection
...
setundef: respect selection for cells, processes, and connections
2026-03-18 22:53:06 +00:00
Emil J. Tywoniak
ad7a776d73
genrtlil: even faster removeSignalFromCaseTree
2026-03-18 23:33:35 +01:00
Emil J. Tywoniak
27737c6e2e
rtlil: add remove2 unit test
2026-03-18 23:33:35 +01:00
Emil J. Tywoniak
ea11453cef
rtlil: faster remove2
2026-03-18 23:33:35 +01:00
Emil J. Tywoniak
23ce4b8560
genrtlil: faster removeSignalFromCaseTree
2026-03-18 23:33:35 +01:00
Miodrag Milanović
a141bd941c
Merge pull request #5761 from YosysHQ/fix_ci
...
Check results properly
2026-03-18 20:08:04 +00:00
Miodrag Milanović
4a6bd6a2fe
Merge pull request #5762 from YosysHQ/revert-5758-lofty/abc-refactor-1
...
Revert "abc: remove -fast [sc-269]"
2026-03-18 17:57:53 +00:00
Lofty
f9d930ba5a
Revert "abc: remove -fast [sc-269]"
2026-03-18 17:55:17 +00:00
Lofty
c4cc53a72e
synth: fix after abc -fast removal
2026-03-18 17:59:58 +01:00
Miodrag Milanovic
bccfdef05d
Check results properly
2026-03-18 17:48:28 +01:00
Lofty
e05ed6b850
Merge pull request #5758 from YosysHQ/lofty/abc-refactor-1
...
abc: remove -fast [sc-269]
2026-03-18 15:09:36 +00:00
Lofty
18a7c54ebd
Merge pull request #5756 from YosysHQ/lofty/abc9-refactor-2
...
abc9: cleanup commented code [sc-269]
2026-03-18 14:46:06 +00:00
Lofty
0b3f103745
abc: remove -S
2026-03-18 14:40:23 +00:00
Lofty
93c762c7c1
abc9: remove abc9.if.C
2026-03-18 14:27:27 +00:00
Lofty
926814f1e4
abc9: cleanup commented code
2026-03-18 14:16:31 +00:00
Lofty
0ea739b7d9
abc: remove -fast
2026-03-18 14:15:42 +00:00
Lofty
150860c1c3
Merge pull request #5755 from YosysHQ/lofty/abc9-refactor-1
...
abc9_exe: fix typo
2026-03-18 12:25:44 +00:00
Lofty
e78690fc47
abc9_exe: fix typo
2026-03-18 11:44:13 +00:00
Emil J
c8f715fed8
Merge pull request #5664 from rocallahan/parallel-opt-clean
...
Parallelize `opt_clean` pass
2026-03-16 09:52:34 +00:00
Miodrag Milanović
06264cdb2e
Merge pull request #5746 from IAmMarcelJung/fabulous/add_frame_config_mux_bels
...
fabulous: add frame_config_mux BEls
2026-03-16 08:21:01 +00:00
KrystalDelusion
1111a401f7
Merge pull request #5750 from calewis/return_things
...
Fix missing return in NDEBUG case
2026-03-13 22:07:28 +00:00
Drew Lewis
4251cd69ed
Fix missing return in NDEBUG case
...
Signed-off-by: Drew Lewis <cannada@google.com>
2026-03-13 19:51:49 +00:00
Marcel Jung
49ecb1ac11
fabulous: add frame_config_mux BEls
2026-03-12 16:05:21 +01:00
Lofty
4716f4410f
Merge pull request #5741 from YosysHQ/lofty/quicklogic-mul-bugfix
...
synth_quicklogic: fix small multiplier inference
2026-03-11 11:47:46 +00:00
Lofty
53939bd3ba
synth_quicklogic: fix small multiplier inference
2026-03-11 11:14:09 +00:00
Catherine
18d94fe9a4
Merge pull request #5740 from kivikakk/push-utvloulmsuqy
...
cxxrtl: Suppress another un/signed comparison warning!
2026-03-11 10:27:27 +00:00
Asherah Connor
5c74446e57
cxxrtl: Suppress another un/signed comparison warning!
2026-03-11 20:50:09 +11:00
Catherine
4d725ee84d
Merge pull request #5739 from kivikakk/push-nsqznnrrssrn
...
cxxrtl: Suppress un/signed comparison warning; this is positive
2026-03-11 09:00:22 +00:00
Asherah Connor
c5c104f560
cxxrtl: Suppress un/signed comparison warning; this is positive
2026-03-11 18:35:48 +11:00
Miodrag Milanović
de99d67bbd
Merge pull request #5733 from YosysHQ/update_abc
...
Update ABC as per 2026-03-09
2026-03-09 12:42:13 +00:00
Miodrag Milanovic
fea0d18c0a
Update ABC as per 2026-03-09
2026-03-09 13:04:45 +01:00
abhinavputhran
314d01b35f
changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change
2026-03-08 20:14:03 -04:00
abhinavputhran
47c2257f82
setundef: more tests! and wire selection in -init mode
2026-03-08 19:41:31 -04:00
abhinavputhran
c23ba3f917
I think CI runs within the tests directory based on error so I changed the file path
2026-03-08 18:15:35 -04:00
