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7497 commits 93 branches 52 tags 62 MiB
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1462 commits

Author SHA1 Message Date
Eddie Hung 27e5bf5aad Stop trying to be too smart by prematurely optimising 2019-09-26 09:57:11 -07:00
Eddie Hung 35aaa8d73a mul2dsp.v slice names 2019-09-25 22:58:55 -07:00
Eddie Hung 34aa3532fb Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit 2019-09-25 17:26:47 -07:00
Eddie Hung a4238637ac Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" 
This reverts commit 234738b103.
 2019-09-25 17:25:44 -07:00
Eddie Hung f4387e817c Revert "No need for $__mul anymore?" 
This reverts commit 1d875ac76a.
 2019-09-25 17:24:11 -07:00
Eddie Hung 63940913d2 Only wreduce on t:$add 2019-09-25 17:22:04 -07:00
Eddie Hung 234738b103 Remove _TECHMAP_CELLTYPE_ check since all $mul 2019-09-25 16:51:31 -07:00
Eddie Hung 1d875ac76a No need for $__mul anymore? 2019-09-25 14:06:21 -07:00
Eddie Hung 53ea5daa42 Call 'wreduce' after mul2dsp to avoid unextend() 2019-09-25 14:04:36 -07:00
Eddie Hung 93363c94a2 Oops. Actually use __NAME__ in ABC_DSP48E1 macro 2019-09-25 10:33:16 -07:00
Eddie Hung b41d2fb4e4 Add (* techmap_autopurge *) to abc_unmap.v too 2019-09-23 22:02:22 -07:00
Eddie Hung 11ac37733d Add techmap_autopurge to outputs in abc_map.v too 2019-09-23 21:56:28 -07:00
Eddie Hung 27167848f4 Revert "Add a xilinx_finalise pass" 
This reverts commit 23d90e0439.
 2019-09-23 19:52:55 -07:00
Eddie Hung 0f53893104 Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" 
This reverts commit 67c2db3486.
 2019-09-23 19:52:55 -07:00
Eddie Hung 29db96fa1f Revert "Vivado does not like zero width port connections" 
This reverts commit 895e2befa7.
 2019-09-23 19:52:54 -07:00
Eddie Hung 895e2befa7 Vivado does not like zero width port connections 2019-09-23 19:04:07 -07:00
Eddie Hung 67c2db3486 Remove (* techmap_autopurge *) from abc_unmap.v since no effect 2019-09-23 18:56:18 -07:00
Eddie Hung 23d90e0439 Add a xilinx_finalise pass 2019-09-23 18:56:02 -07:00
Eddie Hung 4401e5f142 Grammar 2019-09-20 14:24:31 -07:00
Eddie Hung ab46d9017b Fix signedness bug 2019-09-20 10:11:36 -07:00
Eddie Hung 289cf688b7 Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 2019-09-20 09:02:29 -07:00
Eddie Hung 829e4f5d2c Revert "Move mul2dsp before wreduce" 
This reverts commit e4f4f6a9d5.
 2019-09-20 08:56:16 -07:00
Eddie Hung e4f4f6a9d5 Move mul2dsp before wreduce 2019-09-20 08:41:40 -07:00
Eddie Hung 691686f92c Tidy up, fix undriven 2019-09-19 20:04:52 -07:00
Eddie Hung 1602516a8b $__ABC_REG to have WIDTH parameter 2019-09-19 19:37:45 -07:00
Eddie Hung e09f80479e Fix DSP48E1 timing by breaking P path if MREG or PREG 2019-09-19 18:59:28 -07:00
Eddie Hung 362a803779 Revert "Different approach to timing" 
This reverts commit 41256f48a5.
 2019-09-19 18:33:38 -07:00
Eddie Hung 41256f48a5 Different approach to timing 2019-09-19 18:33:29 -07:00
Eddie Hung 5ca25b0c59 Suppress $anyseq warnings 2019-09-19 16:27:14 -07:00
Eddie Hung 595fb611a5 Use (* techmap_autopurge *) to suppress techmap warnings 2019-09-19 15:58:01 -07:00
Eddie Hung c15a35db84 D is 25 bits not 24 bits wide 2019-09-19 15:55:49 -07:00
Eddie Hung b88f0f6450 Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
Eddie Hung 95db2489bd synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 2019-09-19 14:58:06 -07:00
Eddie Hung 3b9b0fcd06 Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 2019-09-19 14:57:38 -07:00
Marcin Kościelnicki 13fa873f11 Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
Eddie Hung fd3b033903 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-18 12:23:22 -07:00
Eddie Hung 25e0f0c376 Fix copy-paste 2019-09-18 12:19:16 -07:00
Eddie Hung b77cf6ba48 Mis-spell 2019-09-18 11:12:46 -07:00
Eddie Hung e992dbf2c5 Add pattern detection support for DSP48E1 model, check against vendor 2019-09-18 10:45:04 -07:00
Eddie Hung 3ec28ec53a
Merge pull request #1379 from mmicko/sim_models 
Added simulation models for Efinix and Anlogic
 2019-09-18 10:04:27 -07:00
Miodrag Milanovic 3e9449cb0b make note that it is for latch mode 2019-09-18 17:48:16 +02:00
Miodrag Milanovic b0ca6de472 better lut handling 2019-09-18 17:45:19 +02:00
Miodrag Milanovic 8badd4d812 better handling of lut and begin/end add 2019-09-18 17:45:07 +02:00
Marcin Kościelnicki 09ac36da60 xilinx: Make blackbox library family-dependent. 
Fixes #1246.
 2019-09-15 13:37:24 +02:00
Miodrag Milanovic 3487b95224 Added simulation models for Efinix and Anlogic 2019-09-15 09:37:16 +02:00
Eddie Hung 681be20ca2 Add `undef DSP48E1_INST 2019-09-13 17:07:18 -07:00
Eddie Hung 61877e1370 Fix D -> P{,COUT} delay 2019-09-13 13:32:55 -07:00
Eddie Hung d0b202c58d Add no MULT no DPORT config 2019-09-13 12:05:14 -07:00
Eddie Hung 247a63f55d Add support for MULT and DPORT 2019-09-13 11:45:55 -07:00
Eddie Hung e235dd0785 Refine diagram 2019-09-13 09:34:40 -07:00