Map $macc_v2 cells (one signed <=27x18 product + one <=48-bit addend)
to MULTALU27X18 with the C addend enabled, so a*b+c maps to a single
DSP block instead of a multiply + fabric adder.
The C addend requires DYN_C_SEL("TRUE") + CSEL=1 (gowin_pack reads the
CSEL port, not the C_SEL parameter).
alumacc + macc techmap run before wreduce for gw5a, so $mul and $add
ports still have matching widths when alumacc tries to merge them.
Running after wreduce breaks the merge: wreduce narrows $mul Y (48->45)
but not $add A (stays 48), and alumacc can't merge mismatched widths.
Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.
Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).
To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.
Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
- functions that have a const `[]` operator method now support `__getitem__` in Python
- fields of a pointer type now return a `reference_internal` instead of a `copy` because classes referenced to by pointers typically aren't copyable (e.g. RTLIL::Wire, RTLIL::Module, etc)
- removed duplicate of test_script.py
