Emil J. Tywoniak
20b2e47b42
verilog_location: rename location to Location to avoid conflict with Pass::location
2025-08-08 16:22:54 +02:00
Emil J. Tywoniak
65b53e6473
fixup! ast: fix import node
2025-08-08 16:19:18 +02:00
Emil J. Tywoniak
a5228e5bb0
ast: fix import node
2025-08-08 16:15:20 +02:00
Emil J. Tywoniak
72ff18bab0
verilog_lexer: refactor
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
d49546b36e
ast: refactor
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
90e3579820
ast: remove null_check as dead code
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
1a4dd18c5f
simplify: simplify
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
581b9684a2
simplify: std::gcd
2025-08-08 15:36:43 +02:00
Krystine Sherwin
950339b1b0
simplify.cc: Drop unused debug prints
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At least the ones added by this PR. There are some unused debug prints that are *changed* by this PR, but I've left them.
2025-08-08 15:36:43 +02:00
Krystine Sherwin
c12cd1f4fb
frontends/ast: More usage of auto
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For consistency.
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
2f78d9330a
preproc: formatting
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
0f2ab91952
verilog_lexer, verilog_parser: remove comment
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
39a44c3539
verilog_lexer: fix fallthrough warning
2025-08-08 15:36:43 +02:00
Emil J
2231834f34
verilog_lexer: remove comment
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Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
9d35b0bf4a
preproc: formatting
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
b0e3e99766
verilog: fix build dependency graph
2025-08-08 15:36:43 +02:00
Gary Wong
9f022f01da
verilog: add support for SystemVerilog string literals.
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Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-08-08 15:36:43 +02:00
garytwong
5240a63353
verilog: fix string literal regular expression ( #5187 )
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* verilog: fix string literal regular expression.
A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.
* verilog: add regression test for string literal regex bug.
Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af40aa7eaf
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
9630663459
read_verilog, ast: use unified locations in errors and simplify dependencies
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
e090db4ebc
readme, verilog_parser: bison 3.8 and ubuntu 22.04 example
2025-08-08 15:36:43 +02:00
Krystine Sherwin
3aa1c1abe6
dpicall.cc: Fix sans-plugin function call
2025-08-08 15:36:43 +02:00
Krystine Sherwin
a7c80ffe5f
preproc.cc: Use full path for generated file
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Fixes out-of-tree builds.
2025-08-08 15:36:43 +02:00
Krystine Sherwin
fc0be83d7f
preproc depends on parser
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
e3fd310830
fixup! fixup! ast, read_verilog: unify location types, reduce filename copying
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
4509446c72
fixup! ast, read_verilog: unify location types, reduce filename copying
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
2a9102565f
ast, read_verilog: unify location types, reduce filename copying
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
041599b7d9
neater errors, lost in the sauce of source
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
a6293df781
ast, read_verilog: refactoring
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
51fc94cf2d
ast: fix new memory safety bugs from rebase
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
b7b3caa475
ast: ownership for string values
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
dfcef88310
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-08-08 15:36:42 +02:00
Emil J. Tywoniak
070a758248
Revert "verilog: fix string literal regular expression ( #5187 )"
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This reverts commit 834a7294b7
2025-08-08 15:35:08 +02:00
Emil J. Tywoniak
5ae0120134
Revert "verilog: add support for SystemVerilog string literals."
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This reverts commit 5feb1a1752
2025-08-08 15:35:08 +02:00
Emil J. Tywoniak
8a76eba891
Revert "verilog: fix parser "if" memory errors."
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This reverts commit 34a2abeddb
2025-08-08 15:35:08 +02:00
KrystalDelusion
7f0e864d44
Merge pull request #5265 from bhagwat-rahul/fix-package-import
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Support package import
2025-08-08 09:32:54 +12:00
Rahul Bhagwat
f12055d3e0
rm debug logs
2025-08-06 15:39:36 -04:00
Rahul Bhagwat
7e0157ba2b
fix whitespace issues
2025-08-06 15:32:36 -04:00
Rahul Bhagwat
fe59b6d3db
add safety checks and better name matching
2025-08-04 20:57:43 -04:00
Jannis Harder
75b62d0164
verificsva: Fix typo in the cover only followed-by operator support
2025-08-04 15:38:19 +02:00
Rahul Bhagwat
761015b23e
add separate module test
2025-08-03 23:48:33 -04:00
Rahul Bhagwat
b776283d79
implement package import
2025-08-03 23:31:54 -04:00
Miodrag Milanovic
f92a53ec31
verific: handle nullptr for message_id
2025-07-30 10:51:54 +02:00
Mike Inouye
0314db80ea
Correctly reset Verific flags to Yosys defaults after -import and warn this has occurred.
...
Co-authored-by: Chris Pearce <chris@pearce.org.nz>
Signed-off-by: Mike Inouye <mikeinouye@google.com>
2025-07-25 19:15:01 +00:00
KrystalDelusion
5b8b5292ee
Merge pull request #4959 from YosysHQ/krys/primitive_array_error
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simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
2025-07-21 10:26:00 +12:00
N. Engelhardt
e47f5369fd
verificsva: check -L value is small enough for code to work
2025-07-09 15:58:35 +02:00
KrystalDelusion
1a215719e5
Merge pull request #5192 from garytwong/multiline-string
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verilog: support newline and hex escapes in string literals
2025-07-08 10:27:01 +12:00
N. Engelhardt
642756a9c6
Merge pull request #5178 from jix/sva_cover_only_followed_by
2025-07-07 10:07:06 +02:00
Gary Wong
5feb1a1752
verilog: add support for SystemVerilog string literals.
...
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
Miodrag Milanovic
eed3bc243f
verific: enable replacing const exprs in static elaboration by default
2025-07-02 11:54:19 +02:00
N. Engelhardt
7b0c1fe491
Merge pull request #5102 from YosysHQ/krys/verilog_no_select
2025-06-30 13:35:17 +00:00
