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add separate module test

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Rahul Bhagwat 2025-08-03 23:48:33 -04:00
parent b776283d79
commit 761015b23e
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4 changed files with 54 additions and 3 deletions
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20
frontends/ast/simplify.cc
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@ -1109,10 +1109,24 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (child->type == AST_IMPORT) {
// Find the package in the design
AstNode *package_node = nullptr;
// First look in current_ast->children (for packages in same file)
for (auto &design_child : current_ast->children) {
if (design_child->type == AST_PACKAGE && design_child->str == child->str) {
package_node = design_child;
break;
if (design_child->type == AST_PACKAGE) {
if (design_child->str == child->str) {
package_node = design_child;
break;
}
}
}
// If not found, look in design->verilog_packages (for packages from other files)
if (!package_node && simplify_design_context != nullptr) {
for (auto &design_package : simplify_design_context->verilog_packages) {
if (design_package->str == child->str) {
package_node = design_package;
break;
}
}
}

13
tests/verilog/package_import_separate.sv Normal file
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@ -0,0 +1,13 @@
package config_pkg;
localparam integer
DATA_WIDTH = 8,
ADDR_WIDTH = 4;
localparam logic [2:0]
IDLE = 3'b000,
START = 3'b001,
DATA = 3'b010,
ODD_PARITY = 3'b011,
STOP = 3'b100,
DONE = 3'b101;
endpackage

5
tests/verilog/package_import_separate.ys Normal file
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@ -0,0 +1,5 @@
read_verilog -sv package_import_separate.sv
read_verilog -sv package_import_separate_module.sv
hierarchy -check
proc
opt -full

19
tests/verilog/package_import_separate_module.sv Normal file
View file

@ -0,0 +1,19 @@
import config_pkg::*;
module top;
logic [DATA_WIDTH-1:0] data;
logic [ADDR_WIDTH-1:0] addr;
logic [2:0] state;
always_comb begin
case (state)
IDLE: data = 8'h00;
START: data = 8'h01;
DATA: data = 8'h02;
ODD_PARITY: data = 8'h03;
STOP: data = 8'h04;
DONE: data = 8'h05;
default: data = 8'hFF;
endcase
end
endmodule