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frontends/ast: More usage of auto
For consistency.
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01b14061ed
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2 changed files with 17 additions and 17 deletions
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@ -2086,7 +2086,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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cell->set_bool_attribute(ID::module_not_derived);
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for (auto it = children.begin(); it != children.end(); it++) {
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AstNode *child = it->get();
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auto* child = it->get();
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if (child->type == AST_CELLTYPE) {
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cell->type = child->str;
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if (flag_icells && cell->type.begins_with("\\$"))
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@ -2095,7 +2095,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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if (child->type == AST_PARASET) {
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IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
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const AstNode *value = child->children[0].get();
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const auto* value = child->children[0].get();
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if (value->type == AST_REALVALUE)
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log_file_warning(*location.begin.filename, location.begin.line, "Replacing floating point parameter %s.%s = %f with string.\n",
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log_id(cell), log_id(paraname), value->realvalue);
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@ -2108,7 +2108,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (child->type == AST_ARGUMENT) {
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RTLIL::SigSpec sig;
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if (child->children.size() > 0) {
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AstNode *arg = child->children[0].get();
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auto* arg = child->children[0].get();
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int local_width_hint = -1;
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bool local_sign_hint = false;
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// don't inadvertently attempt to detect the width of interfaces
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@ -698,13 +698,13 @@ static bool contains_unbased_unsized(const AstNode *node)
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// dimensions of the given wire reference
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void add_wire_for_ref(location loc, const RTLIL::Wire *ref, const std::string &str)
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{
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std::unique_ptr<AstNode> left = AstNode::mkconst_int(loc, ref->width - 1 + ref->start_offset, true);
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std::unique_ptr<AstNode> right = AstNode::mkconst_int(loc, ref->start_offset, true);
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auto left = AstNode::mkconst_int(loc, ref->width - 1 + ref->start_offset, true);
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auto right = AstNode::mkconst_int(loc, ref->start_offset, true);
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if (ref->upto)
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std::swap(left, right);
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std::unique_ptr<AstNode> range = std::make_unique<AstNode>(loc, AST_RANGE, std::move(left), std::move(right));
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auto range = std::make_unique<AstNode>(loc, AST_RANGE, std::move(left), std::move(right));
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std::unique_ptr<AstNode> wire = std::make_unique<AstNode>(loc, AST_WIRE, std::move(range));
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auto wire = std::make_unique<AstNode>(loc, AST_WIRE, std::move(range));
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wire->is_signed = ref->is_signed;
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wire->is_logic = true;
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wire->str = str;
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@ -821,8 +821,8 @@ static bool try_determine_range_width(AstNode *range, int &result_width)
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return true;
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}
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std::unique_ptr<AstNode> left_at_zero_ast = range->children[0]->clone_at_zero();
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std::unique_ptr<AstNode> right_at_zero_ast = range->children[1]->clone_at_zero();
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auto left_at_zero_ast = range->children[0]->clone_at_zero();
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auto right_at_zero_ast = range->children[1]->clone_at_zero();
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while (left_at_zero_ast->simplify(true, 1, -1, false)) {}
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while (right_at_zero_ast->simplify(true, 1, -1, false)) {}
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@ -1575,7 +1575,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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if (children[0]->type == AST_WIRE) {
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int width = 1;
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std::unique_ptr<AstNode> node;
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AstNode* child = children[0].get();
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auto* child = children[0].get();
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if (child->children.size() == 0) {
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// Base type (e.g., int)
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width = child->range_left - child->range_right +1;
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@ -1591,7 +1591,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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if (resolved_type_node->type != AST_TYPEDEF)
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input_error("`%s' does not name a type\n", type_name.c_str());
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log_assert(resolved_type_node->children.size() == 1);
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AstNode *template_node = resolved_type_node->children[0].get();
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auto* template_node = resolved_type_node->children[0].get();
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// Ensure typedef itself is fully simplified
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while (template_node->simplify(const_fold, stage, width_hint, sign_hint)) {};
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@ -2048,7 +2048,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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// Pretend it's just a wire in order to resolve the type in the code block above.
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AstNodeType param_type = type;
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type = AST_WIRE;
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std::unique_ptr<AstNode> expr = std::move(children.front());
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auto expr = std::move(children.front());
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children.erase(children.begin());
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while (is_custom_type && simplify(const_fold, stage, width_hint, sign_hint)) {};
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type = param_type;
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@ -2130,13 +2130,13 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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range_right = children[0]->range_right;
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bool force_upto = false, force_downto = false;
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if (attributes.count(ID::force_upto)) {
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AstNode *val = attributes[ID::force_upto].get();
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auto* val = attributes[ID::force_upto].get();
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if (val->type != AST_CONSTANT)
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input_error("Attribute `force_upto' with non-constant value!\n");
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force_upto = val->asAttrConst().as_bool();
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}
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if (attributes.count(ID::force_downto)) {
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AstNode *val = attributes[ID::force_downto].get();
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auto* val = attributes[ID::force_downto].get();
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if (val->type != AST_CONSTANT)
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input_error("Attribute `force_downto' with non-constant value!\n");
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force_downto = val->asAttrConst().as_bool();
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@ -3307,7 +3307,7 @@ skip_dynamic_range_lvalue_expansion:;
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}
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else
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{
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std::unique_ptr<AstNode>& the_range = children[0]->children[1];
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auto& the_range = children[0]->children[1];
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std::unique_ptr<AstNode> offset_ast;
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int width;
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@ -5165,7 +5165,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
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std::vector<RTLIL::State> x_bits;
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for (int i = 0; i < width; i++)
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x_bits.push_back(RTLIL::State::Sx);
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std::unique_ptr<AstNode> constant = AstNode::mkconst_bits(location, x_bits, false);
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auto constant = AstNode::mkconst_bits(location, x_bits, false);
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constant->cloneInto(*this);
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}
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}
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@ -5427,7 +5427,7 @@ std::unique_ptr<AstNode> AstNode::eval_const_function(AstNode *fcall, bool must_
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while (!block->children.empty())
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{
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// log("%zu left in block %p\n", block->children.size(), block.get());
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std::unique_ptr<AstNode>& stmt = block->children.front();
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auto& stmt = block->children.front();
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#if 0
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log("-----------------------------------\n");
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