Miodrag Milanović
c8adb5a2e2
Merge pull request #4001 from YosysHQ/vhdl_arch
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Preserve VHDL architecture name in attribute
2023-10-13 08:55:26 +02:00
Martin Povišer
62d6338688
quicklogic: Fix pp3 dffs test
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Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
2023-10-12 12:45:40 +02:00
N. Engelhardt
6c562c76bc
fix handling right shifts
2023-10-12 11:46:09 +02:00
N. Engelhardt
2d6d6a8da1
fix handling a_width != y_width
2023-10-12 11:46:09 +02:00
N. Engelhardt
d0e559a34f
celledges: support shift ops
2023-10-12 11:46:09 +02:00
Miodrag Milanovic
d473a207a1
Preserve VHDL architecture name in attribute
2023-10-12 09:17:06 +02:00
github-actions[bot]
59fbee4009
Bump version
2023-10-12 00:13:29 +00:00
Krystine Sherwin
5a7a7b319a
Fix make clean
2023-10-12 05:02:33 +13:00
Krystine Sherwin
ebcbb94a21
Fixing makefile
2023-10-12 04:50:27 +13:00
Miodrag Milanović
417871e831
Merge pull request #3998 from jix/verific-fix-norename
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verific: Use CellBaseName to identify top modules
2023-10-11 11:10:23 +02:00
Krystine Sherwin
8335044c35
docs: reflowing selections doc
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Combined presentation sections with appnote sections.
Moved a bunch of Yosys one-liners in-line.
Better reference in interactive investigation to memdemo as a part of advanced logic cone selection (esp. because the show commands use some of the advanced features)
2023-10-11 12:46:26 +13:00
Krystine Sherwin
c61ab7d627
docs: Tidying interactive investigation
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More :numref: because I figured out they were only failing if I didn't do a full re-make.
Reflow first section a little to help readability.
Also includes a css change to prevent code block caption text from bunching into the caption number.
2023-10-11 11:13:06 +13:00
Jannis Harder
4ed708836a
verific: Use CellBaseName to identify top modules
2023-10-10 11:51:16 +02:00
Krystine Sherwin
9e35848c8e
docs: initial 011 selections move
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Also deleting the 011 document.
2023-10-10 12:36:10 +13:00
Krystine Sherwin
a019c26b9d
docs: Moving 011 into main body of manual
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Mostly in the `more_scripting` section, with part of the intro in the `scripting_intro`.
Also includes an extra todo on the installation page and some extra notes on where to find `show` details where relevant.
2023-10-10 12:35:23 +13:00
Krystine Sherwin
b0f8059bce
Moving images and static folders
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Images now included relative to the `docs/source` folder instead of the rst file.
Also makes sure to add the updated `yosyshq.css` (which as a sidenote has ended up as `custom.css` in most of the other docs).
2023-10-10 10:12:50 +13:00
N. Engelhardt
3e22791810
Merge pull request #3975 from rmlarsen/optmerge
2023-10-09 17:05:19 +02:00
github-actions[bot]
11b9deba9f
Bump version
2023-10-09 00:15:38 +00:00
Lofty
a79b15e947
Merge pull request #3992 from YosysHQ/empty-case-fix
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write_verilog: avoid emitting empty cases.
2023-10-08 08:05:10 +01:00
Wanda
c36cf9c5ac
write_verilog: avoid emitting empty cases.
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The Verilog grammar does not allow an empty case. Most synthesis tools
are quite permissive about this, but Quartus is not. This causes
problems for amaranth with Quartus (see amaranth-lang/amaranth#931 ).
2023-10-08 01:11:30 +02:00
Lofty
a1923a5f77
Merge pull request #3988 from YosysHQ/micko/fix_leak
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Fix readline/editline memory leak
2023-10-07 20:50:01 +01:00
Marcus Comstedt
0ca39e233b
scc: Use hashlib instead of STL for deterministic behaviour
2023-10-07 10:43:00 +02:00
github-actions[bot]
51e9b0882b
Bump version
2023-10-07 00:14:44 +00:00
Rasmus Munk Larsen
bc0df04e06
Get rid of double lookup in TopoSort::node(). This speeds up typical TopoSort time overall by ~10%.
2023-10-06 12:53:05 -07:00
Miodrag Milanovic
2ab7d1d0c8
Fix readline/editline memory leak
2023-10-06 16:05:44 +02:00
Martin Povišer
8367f06188
ast/simplify: Remove unused in_param code
2023-10-05 22:42:36 -04:00
Rasmus Munk Larsen
6a5799cc2e
Add missing initialization of node_cmp_ member.
2023-10-05 17:27:26 -07:00
github-actions[bot]
fc815fdb47
Bump version
2023-10-06 00:14:52 +00:00
Rasmus Munk Larsen
0a37c2a301
Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten.
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Add back statement that inserts nodes in order in opt_expr.cc.
2023-10-05 17:01:42 -07:00
Rasmus Munk Larsen
fd7bd420b3
Add back newline.
2023-10-05 15:26:29 -07:00
Rasmus Munk Larsen
e38c9e01c9
Undo formatting changes in kernel/utils.h.
2023-10-05 15:24:26 -07:00
Miodrag Milanović
a54e6f2d1f
Merge pull request #3984 from YosysHQ/module_hdlname
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verific: save original module name
2023-10-05 19:41:00 +02:00
Martin Povišer
c3fd88624a
sim: Bail on processes
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Instead of silently missimulating, error out when there are processes
found in the simulation hierarchy.
2023-10-05 19:25:17 +02:00
Martin Povišer
a782b15aae
sim: s/instanced/instantiated/
2023-10-05 19:25:17 +02:00
Martin Povišer
6ac43e49bc
sim: Change clocked read port suggestion to memory_nordff
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`memory_nordff` has the advantage that it can be called just ahead of
the simulation step no matter whether the clocked read port has been
inferred or was explicitly instantiated in a flow.
2023-10-05 19:25:17 +02:00
Jannis Harder
6b8203f8a0
Merge pull request #3985 from jix/static-elaboration-top
2023-10-05 17:45:36 +02:00
Jannis Harder
47a4b790f8
verific: Pass top modules to static elaboration when using hierarchy
2023-10-05 16:51:49 +02:00
Jannis Harder
23b9e61c47
verific: Pass list of top modules to static elaboration
2023-10-05 16:51:49 +02:00
Miodrag Milanovic
268fe92d22
verific: save original module name
2023-10-05 11:22:40 +02:00
Miodrag Milanovic
824fdaadf6
mingw build fix
2023-10-05 09:55:53 +02:00
Miodrag Milanovic
b88f7fc6e8
Next dev cycle
2023-10-05 09:16:05 +02:00
Miodrag Milanovic
4a1b559925
Release version 0.34
2023-10-05 09:14:12 +02:00
Miodrag Milanović
881ce80a11
Merge pull request #3982 from povik/booth-fix
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booth: Fix vacancy check when summing down result
2023-10-05 08:15:45 +02:00
Martin Povišer
4506e11d0f
booth: Extend test to catch bug from previous commit
2023-10-04 23:30:29 +02:00
Martin Povišer
0434f9d3d1
booth: Fix vacancy check when summing down result
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In commit fedd12261
2023-10-04 23:21:40 +02:00
Lofty
3e02b63ee1
Merge pull request #3977 from YosysHQ/lofty/gowin-dff
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gowin: fix abc9 attributes and specify blocks
2023-10-04 05:18:59 +01:00
github-actions[bot]
f00d6f3c12
Bump version
2023-10-04 00:15:12 +00:00
Lofty
294844137b
gowin: fix abc9 attributes and specify blocks
2023-10-04 00:16:10 +01:00
Rasmus Munk Larsen
57a2b4b0cd
Explicitly use uint64_t as the type of fingerprint to avoid type mismatch with some compilers.
2023-10-03 15:02:02 -07:00
Rasmus Munk Larsen
8e0308b5e7
Revert changes to celltypes.h. Use dict instead of std::unordered_map and most hash function for uint64_t to hashlib.h to support this.
2023-10-03 14:25:59 -07:00
