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fix handling a_width != y_width

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This commit is contained in:
N. Engelhardt 2023-10-02 17:29:09 +02:00
parent d0e559a34f
commit 2d6d6a8da1
1 changed files with 6 additions and 5 deletions
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11
kernel/celledges.cc
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@ -174,24 +174,25 @@ void demux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int width = GetSize(cell->getPort(ID::A));
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int y_width = GetSize(cell->getPort(ID::Y));
for (int i = 0; i < width; i++){
for (int i = 0; i < y_width; i++){
for (int k = 0; k < b_width; k++)
db->add_edge(cell, ID::B, k, ID::Y, i, -1);
if (cell->type.in(ID($shl), ID($sshl))) {
for (int k = i; k >= 0; k--)
for (int k = min(i, a_width); k >= 0; k--)
db->add_edge(cell, ID::A, k, ID::Y, i, -1);
}
if (cell->type.in(ID($shr), ID($sshr)))
for (int k = i; k < width; k++)
for (int k = i; k < a_width; k++)
db->add_edge(cell, ID::A, k, ID::Y, i, -1);
if (cell->type.in(ID($shift), ID($shiftx)))
for (int k = 0; k < width; k++)
for (int k = 0; k < a_width; k++)
db->add_edge(cell, ID::A, k, ID::Y, i, -1);
}
}