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Merge pull request #3992 from YosysHQ/empty-case-fix
write_verilog: avoid emitting empty cases.
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commit
a79b15e947
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@ -2008,6 +2008,11 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
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dump_case_body(f, indent + " ", *it);
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}
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if (sw->cases.empty()) {
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// Verilog does not allow empty cases.
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f << stringf("%s default: ;\n", indent.c_str());
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}
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f << stringf("%s" "endcase\n", indent.c_str());
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}
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