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Merge pull request #3982 from povik/booth-fix
booth: Fix vacancy check when summing down result
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commit
881ce80a11
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@ -533,7 +533,7 @@ struct BoothPassWorker {
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// get the bits in this column.
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SigSpec column_bits;
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for (int row_ix = 0; row_ix < row_size; row_ix++) {
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if (bits_to_reduce[row_ix][column_ix].wire)
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if (bits_to_reduce[row_ix][column_ix] != State::S0)
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column_bits.append(bits_to_reduce[row_ix][column_ix]);
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}
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for (auto c : carry_bits_to_add_to_next_column) {
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@ -750,7 +750,7 @@ struct BoothPassWorker {
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SigSpec first_csa_ips;
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// get the first 3 inputs, if possible
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for (var_ix = 0; var_ix < column_bits.size() && first_csa_ips.size() != 3; var_ix++) {
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if (column_bits[var_ix].is_wire())
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if (column_bits[var_ix] != State::S0)
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first_csa_ips.append(column_bits[var_ix]);
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}
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@ -782,7 +782,7 @@ struct BoothPassWorker {
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// get the next two variables to sum
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for (; var_ix <= column_bits.size() - 1 && csa_ips.size() < 2;) {
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// skip any empty bits
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if (column_bits[var_ix].is_wire())
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if (column_bits[var_ix] != State::S0)
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csa_ips.append(column_bits[var_ix]);
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var_ix++;
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}
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@ -1 +1,15 @@
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test_cell -s 1694091355 -n 100 -script booth_map_script.ys_ $mul
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read_verilog <<EOF
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module test(clk, a, b, y);
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input wire clk;
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input wire [9:0] a;
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input wire [6:0] b;
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output wire [20:0] y;
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assign y = a * b;
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endmodule
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EOF
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booth
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sat -verify -set a 0 -set b 0 -prove y 0
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design -reset
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test_cell -s 1694091355 -n 100 -script booth_map_script.ys_ $mul
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