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Code Activity
15694 commits 122 branches 59 tags 73 MiB
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4565 commits

Author SHA1 Message Date
Martin Povišer
00e899f98d booth: Refactor signed multiplier full adders emission 2023-11-22 12:46:15 +01:00
N. Engelhardt
63cec22a0c
Merge pull request #3883 from phsauter/peepopt-shiftadd 
peepopt: Add `shiftadd` pattern
 2023-11-07 10:42:15 +01:00
phsauter
3618294bac peepopt: Add assert of consistent shiftadd data 2023-11-06 16:35:00 +01:00
Philippe Sauter
b6df900bcc peepopt: Describe shiftadd rule in help message 2023-11-06 14:01:37 +01:00
phsauter
9ca57d9f13 peepopt: fix and refactor shiftadd 
- moved all selection and filtering logic to the match block
- applied less-verbose code suggestions
- removed constraint on number of bits in shift-amount
- added check for possible wrap-arround in the operation
 2023-11-06 14:01:37 +01:00
Philippe Sauter
72c6a01e67 peepopt: Add initial shiftadd pattern 2023-11-06 14:01:37 +01:00
N. Engelhardt
080da693d1 memory_libmap: update search order for attributes 2023-10-24 13:55:45 +02:00
N. Engelhardt
1b6d1e9419 memory_libmap: look for ram_style attributes on surrounding signals 2023-10-19 19:23:35 +02:00
Lofty
d21c464ae4
Merge pull request #3946 from rmlarsen/toposort 
Speed up TopoSort by 2.7-3.3x.
 2023-10-17 13:00:18 +01:00
Claire Xen
a4951a3a97
Merge pull request #3986 from povik/sim-ui-fixes 
Slightly improve `sim` UI
 2023-10-16 16:54:05 +02:00
N. Engelhardt
a2f59cf911
Merge pull request #3990 from zeldin/deterministic_scc 2023-10-16 16:51:54 +02:00
Martin Povišer
d6d1cc705e pmgen: Fix sample syntax 2023-10-16 14:19:15 +02:00
Martin Povišer
660be4a31e peepopt: Describe rules in help message 2023-10-16 14:19:15 +02:00
Martin Povišer
5c0c8251c3 peepopt: Remove broken -generate option 2023-10-16 14:19:10 +02:00
Martin Povišer
aa9b86aeec peepopt: Add left-shift 'shiftmul' variant 
Add a separate shiftmul pattern to match on left shifts which implement
demuxing. This mirrors the right shift pattern matcher but is probably
best kept separate instead of merging the two into a single matcher.
In any case the diff of the two matchers should be easily readable.
 2023-10-16 13:52:38 +02:00
Martin Povišer
038a5e1ed4 peepopt: Support shift amounts zero-padded from below 
The `opt_expr` pass running before `peepopt` can interfere with the
detection of a shiftmul pattern due to some of the bottom bits of the
shift amount being replaced with constant zero. Extend the detection to
cover those situations as well.
 2023-10-16 13:52:06 +02:00
Martin Povišer
dd1a8ae49a peepopt: Try to use original wires 2023-10-16 13:52:06 +02:00
Martin Povišer
bd8a81a907 peepopt: Clean up 'shiftmul' a bit 
No functional change intended.
 2023-10-16 13:52:06 +02:00
Martin Povišer
a0c3be3aae peepopt: Drop unused 'initbits' code 
Drop code that was once used by the 'dffmux' pattern but now is unused
after that pattern has been obsoleted by the 'opt_dff' pass.
 2023-10-16 13:52:06 +02:00
N. Engelhardt
6c562c76bc fix handling right shifts 2023-10-12 11:46:09 +02:00
N. Engelhardt
3e22791810
Merge pull request #3975 from rmlarsen/optmerge 2023-10-09 17:05:19 +02:00
Marcus Comstedt
0ca39e233b scc: Use hashlib instead of STL for deterministic behaviour 2023-10-07 10:43:00 +02:00
Rasmus Munk Larsen
0a37c2a301 Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten. 
Add back statement that inserts nodes in order in opt_expr.cc.
 2023-10-05 17:01:42 -07:00
Martin Povišer
c3fd88624a sim: Bail on processes 
Instead of silently missimulating, error out when there are processes
found in the simulation hierarchy.
 2023-10-05 19:25:17 +02:00
Martin Povišer
a782b15aae sim: s/instanced/instantiated/ 2023-10-05 19:25:17 +02:00
Martin Povišer
6ac43e49bc sim: Change clocked read port suggestion to memory_nordff 
`memory_nordff` has the advantage that it can be called just ahead of
the simulation step no matter whether the clocked read port has been
inferred or was explicitly instantiated in a flow.
 2023-10-05 19:25:17 +02:00
Martin Povišer
0434f9d3d1 booth: Fix vacancy check when summing down result 
In commit fedd12261 ("booth: Move away from explicit `Wire` pointers")
a bug was introduced when checking for vacant slots in arrays holding
some intermediate results. Non-wire SigBit values were taken to imply
a vacant slot, but actually a constant one can make its way into those
results, if the multiplier cell configuration is just right. Fix the
vacancy check to address the bug.
 2023-10-04 23:21:40 +02:00
Rasmus Munk Larsen
57a2b4b0cd Explicitly use uint64_t as the type of fingerprint to avoid type mismatch with some compilers. 2023-10-03 15:02:02 -07:00
Rasmus Munk Larsen
8e0308b5e7 Revert changes to celltypes.h. Use dict instead of std::unordered_map and most hash function for uint64_t to hashlib.h to support this. 2023-10-03 14:25:59 -07:00
Martin Povišer
1f1f43edd9 equiv_simple: Fix seed handling in non-short mode 2023-10-03 13:05:42 +02:00
Martin Povišer
dbf11da50a equiv_simple: Do not special-case flip-flop types in cone expansion 
If there's an asynchronous flip-flop type, it will be caught by not
having a synchronous SAT model later on. Otherwise we can support all
flip-flops.
 2023-10-03 13:05:42 +02:00
Martin Povišer
26644ea779 equiv_simple: Drop hollow conditional 
All the listed flip-flop types would be known cells, so the extra part
of the conditional is without effect.
 2023-10-03 13:05:42 +02:00
Rasmus Munk Larsen
bce984fa60 Speed up OptMergePass by 1.7x. 
The main speedup comes from swithing from using a SHA1 hash to std::hash<std::string>. There is no need to use an expensive cryptographic hash for fingerprinting in this context.
 2023-10-02 15:57:18 -07:00
Rasmus Munk Larsen
1bbc12f389 Revert changes to techmap.cc. 2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen
67f1700486 Revert formatting changes. 2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen
abd9c51963 Speed up simplemap_map by 11.6x by directly inserting the cell source attribute in the new object's 'attributes' map instead of calling set_attr_pool to create a new pool and then copying that. Based on a suggestion by Martin Poviser in a comment on https://github.com/YosysHQ/yosys/pull/3959 2023-10-02 17:32:56 +01:00
Jannis Harder
8b42abee50
Merge pull request #3961 from jix/dft-fixes 2023-10-02 16:58:15 +02:00
Jannis Harder
ecf09b9271
Merge pull request #3962 from jix/sim-noinitstate 2023-10-02 16:57:46 +02:00
N. Engelhardt
dcb600ab81
Merge pull request #3938 from povik/booth-cleanup 2023-10-02 16:10:17 +02:00
Jannis Harder
5daa49bafb dft_tag: Fix size extending $x[n]or and $reduce_{or,bool}/$logic_not 2023-09-28 17:33:55 +02:00
Jannis Harder
7eaa4bcb46 sim: Add -noinitstate option and handle non-cosim initstate 
This adds the -noinitstate option which is required to simulate
counterexamples to induction with yw-cosim. Also add handling for
$initstate cells for non-co-simulation.
 2023-09-28 17:29:24 +02:00
Martin Povišer
6b70b3dbef booth: Fix assertion 
Fix assertion to what it should be per Andy's comments.
 2023-09-28 11:50:57 +02:00
N. Engelhardt
3319fdc46e show: use dot for wire aliases instead of BUF 2023-09-25 17:20:16 +02:00
Martin Povišer
91bcf81dbd booth: Note down debug prints are broken 2023-09-25 14:51:26 +02:00
Martin Povišer
7179e4f4b8 booth: Improve user interface 2023-09-25 14:50:41 +02:00
Martin Povišer
cde2a0b926 booth: Make more use of appropriate helpers 
Use the `addFa` helper, do not misuse `new_id` and make other changes
to the transformation code.
 2023-09-25 14:50:41 +02:00
Martin Povišer
62302f601d booth: Remove more of unused helpers 2023-09-25 14:50:41 +02:00
Martin Povišer
30f8387b75 booth: Rewrite the main cell selection loop 2023-09-25 14:50:41 +02:00
Martin Povišer
986507f95f booth: Streamline the low-level circuit emission 
For the basic single-bit operations, opt for gate cells (`$_AND_` etc.)
instead of the coarse cells (`$and` etc.). For the emission of cells
move to the conventional module methods (`module->addAndGate`) away
from the local helpers. While at it, touch on the surrounding code.
 2023-09-25 14:50:41 +02:00
Martin Povišer
cb05262fc4 booth: Remove now-unused helpers 2023-09-25 14:50:41 +02:00