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	peepopt: Try to use original wires
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					 1 changed files with 5 additions and 1 deletions
				
			
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			@ -42,7 +42,11 @@ match mul
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	define <IdString> varport (constport == \A ? \B : \A)
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	set mul_const port(mul, constport).as_const()
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	set mul_din port(mul, varport)
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	// get mul_din unmapped (so no `port()` shorthand)
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	// because we will be using it to set the \A port
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	// on the shift cell, and we want to stay close
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	// to the original design
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	set mul_din mul->getPort(varport)
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endmatch
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code
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