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Author	SHA1	Message	Date
Bogdan Vukobratovic	291b36afeb	Some cleanup, revert sat.cc	2019-06-14 11:35:45 +02:00
Eddie Hung	bc22e2e3ee	Optimise some more	2019-06-13 17:02:58 -07:00
Eddie Hung	d09d4e0706	Move ConstEvalAig to aigerparse.cc	2019-06-13 16:28:11 -07:00
Eddie Hung	75d89e56cf	Fix name clash	2019-06-13 14:27:07 -07:00
Eddie Hung	63e2f83632	More slimming	2019-06-13 13:29:03 -07:00
Eddie Hung	d39a5a77a9	Add ConstEvalAig specialised for AIGs	2019-06-13 13:13:48 -07:00
Bogdan Vukobratovic	8665f48879	Implement disconnection of constant register bits	2019-06-13 19:35:37 +02:00
Eddie Hung	7f9d2d1825	Update CHANGELOG with "synth -abc9"	2019-06-13 09:15:30 -07:00
Eddie Hung	2052806d33	Fix LP SB_LUT4 timing	2019-06-13 08:24:33 -07:00
Eddie Hung	9d34cea65a	More accurate CHANGELOG	2019-06-13 08:22:22 -07:00
Bogdan Vukobratovic	4912567cbf	Pass SigBit by value to Netlist algorithms	2019-06-13 15:42:45 +02:00
Serge Bazanski	d4f77d408c	Merge pull request #829 from abdelrahmanhosny/master ... Dockerfile for Yosys	2019-06-13 12:14:37 +02:00
Eddie Hung	c04482b077	Update CHANGELOG	2019-06-12 16:54:12 -07:00
Eddie Hung	2c40b66785	Rip out all non FPGA stuff from abc9	2019-06-12 16:53:12 -07:00
Eddie Hung	f81a189fb8	Fix spelling	2019-06-12 16:52:09 -07:00
Eddie Hung	90dc4d82de	Revert "For 'stat' do not count modules with abc_box_id" ... This reverts commit b89bb74452.	2019-06-12 16:51:37 -07:00
Eddie Hung	9f275c1437	Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" ... This reverts commit 2223ca91b0, reversing changes made to eaee250a6e.	2019-06-12 16:33:05 -07:00
Eddie Hung	009255d11d	Move neg-pol to pos-pol mapping from ff_map to cells_map.v	2019-06-12 16:07:24 -07:00
Eddie Hung	b3faf0246d	Be more precise when connecting during ABC9 re-integration	2019-06-12 16:04:33 -07:00
Eddie Hung	8374eb1cb4	Remove unnecessary undriven_bits.insert	2019-06-12 15:55:02 -07:00
Eddie Hung	2e7e73f483	Remove hacky wideports_split from abc9	2019-06-12 15:52:49 -07:00
Eddie Hung	d9974b85e7	Fix compile errors when #if 1 for debug	2019-06-12 15:47:39 -07:00
Eddie Hung	342fc0a600	parse_xaiger to cope with inouts	2019-06-12 15:45:46 -07:00
Eddie Hung	fb2758aade	write_xaiger to preserve POs even if driven by constant	2019-06-12 15:44:30 -07:00
Eddie Hung	2e7b3eee40	Add a couple more tests	2019-06-12 15:43:43 -07:00
Bogdan Vukobratovic	d69989b8d2	Rename satgen_algo.h -> algo.h, code cleanup and refactoring	2019-06-12 19:35:05 +02:00
Eddie Hung	8bb67fa67c	Do not call abc9 if no outputs	2019-06-12 10:18:44 -07:00
Eddie Hung	14e870d4c4	More write_xaiger cleanup	2019-06-12 10:00:57 -07:00
Eddie Hung	4be417f6e1	Cleanup write_xaiger	2019-06-12 09:53:14 -07:00
Eddie Hung	b21d29598a	Consistency	2019-06-12 09:40:51 -07:00
Eddie Hung	c7f5091c2f	Reduce diff with master	2019-06-12 09:34:41 -07:00
Eddie Hung	f9433cc34b	Remove abc_flop{,_d} attributes from ice40/cells_sim.v	2019-06-12 09:29:30 -07:00
Eddie Hung	99267f660f	Fix spacing	2019-06-12 09:21:52 -07:00
Eddie Hung	738fdfe8f5	Remove wide mux inference	2019-06-12 09:20:46 -07:00
Eddie Hung	b2c72f74f0	Merge branch 'xc7mux' into xaig	2019-06-12 09:14:27 -07:00
Eddie Hung	7eec64a38f	Merge branch 'xc7mux' of github.com:YosysHQ/yosys into xc7mux	2019-06-12 09:14:12 -07:00
Eddie Hung	afd620fd5f	Typo: wire delay is -W argument	2019-06-12 09:13:53 -07:00
Eddie Hung	2cbcd6224c	Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" ... This reverts commit a138381ac3, reversing changes made to b77c5da769.	2019-06-12 09:05:02 -07:00
Eddie Hung	882a83c383	Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" ... This reverts commit eaee250a6e, reversing changes made to 935df3569b.	2019-06-12 09:04:31 -07:00
Eddie Hung	86efe9a616	Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" ... This reverts commit 2223ca91b0, reversing changes made to eaee250a6e.	2019-06-12 09:01:15 -07:00
Eddie Hung	513c962a71	Merge remote-tracking branch 'origin/xc7mux' into xaig	2019-06-12 08:52:46 -07:00
Eddie Hung	f7a9769c14	Merge remote-tracking branch 'origin/master' into xaig	2019-06-12 08:50:39 -07:00
Eddie Hung	1e838a8913	Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"	2019-06-12 08:49:15 -07:00
Eddie Hung	4c9fde87d1	Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" ... This reverts commit 2dffa4685b.	2019-06-12 08:48:45 -07:00
Eddie Hung	45c2a5f876	Add shregmap -tech xilinx test	2019-06-12 08:34:06 -07:00
Eddie Hung	2dffa4685b	Add "-W' wire delay arg to abc9, use from synth_xilinx	2019-06-11 17:10:47 -07:00
Eddie Hung	6cdea93724	Revert "Try way that doesn't involve creating a new wire" ... This reverts commit 2f427acc9e.	2019-06-11 16:05:42 -07:00
Eddie Hung	d26646051c	Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" ... This reverts commit 5174082208, reversing changes made to 54379f9872.	2019-06-11 16:05:27 -07:00
Eddie Hung	5174082208	Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux	2019-06-11 15:48:41 -07:00
Eddie Hung	2f427acc9e	Try way that doesn't involve creating a new wire	2019-06-11 15:48:20 -07:00